Publicado em: 30/05/2024

IEEE CASS RS Talks 2024

CASS Talks: IA RISC-V Based Processor: Paper-and-Pencil RTL Design and Implementation

No dia 31 de maio às 13:30h (Horário de Brasília) ocorrerá a palestra “IA RISC-V Based Processor: Paper-and-Pencil RTL Design and Implementation” com Prof. Zainalabedin Navabi, do Worcester Polytechnic Institute, USA.

Para acessar a palestra, clique aqui.

Abstract:
Starting with the existing open-source RISC-V Instruction Set Architecture (ISA), this talk discusses our step-by-step experience in design and implementation of a RISC-V processor that we refer to as AFTAB. In an incremental fashion using processor instruction functionalities, we show how the paper-and-pencil design of the processor datapath is done. Similarly, we show how the FSM of the controller is developed in an incremental fashion considering execution of each instruction. Translation of the diagrams obtained during design of datapath and controller to HDL code is the next step in the design process. Following this preliminary HDL description of the processor, we verify our design by simulation. In this simulation design errors are detected and corrections are incorporated in the processor datapath and controller. The next phase is the synthesis process and further functional and timing evaluation of the post-synthesis description of the processor. This phase also affects the hand generated datapath and controller designs. After validation of the design of the base-processor, interrupt handelling, security features, and other extensions are added to the processor hardware.
The work presented here shows our approach for going from ISA of RISC-V to a working chip. Complete documentation along with VHDL description for simulation and FPGA prototyping are available on GitHub.

Short CV:
Dr. Zainalabedin Navabi is an adjunct professor of electrical and computer engineering at Worcester Polytechnic Institute, and professor of ECE at the University of Tehran. He is the author of several textbooks and computer-based trainings on VHDL, Verilog and related tools and environments. Dr. Navabi’s involvement with hardware description languages (HDL) begins in 1976, when he started formal definition of a register transfer level HDL and development of a simulator for it. In 1981 he completed the development of a synthesis tool for that same HDL. The synthesis tool generated MOS layout from an RTL description. Since 1981, Dr. Navabi has been involved in the design, definition, and implementation of Hardware Description Languages and design methodologies. His work on HDLs has continued to languages used today for system-level design and modeling and language-based design space exploration (DSE) methodologies. New domain-specific languages and methodologies for AI and ML
are part of his on-going work.