Publicado em: 29/04/2025

IEEE CASS RS Talks 2025

CASS Talks: High-Speed Wireline Interconnects: Design Challenges and Innovations in 224G SerDes

No dia 2 de maio de 2025, às 13:30 (Horário de Brasília, GMT-3), ocorrerá a palestra “High-Speed Wireline Interconnects: Design Challenges and Innovations in 224G SerDes”, como parte do IEEE CASS RS Talks 2025. Ministrada por Noman Hai, da Synopsys, Canadá, a apresentação discutirá os principais desafios e as soluções inovadoras envolvidas no desenvolvimento da próxima geração de transceptores SerDes de altíssima velocidade.

A palestra será transmitida ao vivo pelo YouTube, no canal oficial do IEEE CASS.

Abstract:
The demand for higher bandwidth in networking, cloud computing, and hyperscale data centers continues to accelerate, driving the evolution of wireline SerDes transceivers. As the industry transitions from 25T to 100T switching capacity, 112G SerDes is making way for next generation 224G architectures. Simultaneously, the rapid expansion of Large Language Models (LLMs) in AI and High-Performance Computing (HPC) is pushing interconnect technology to its limits, with accelerator-to-accelerator communication increasingly dependent on high-bandwidth, low-latency solutions. This talk will explore the present and future of SerDes transceivers, focusing on the design challenges and innovations enabling 224G technology. It will include insights into block diagrams and circuit implementations from Synopsys’ 224G SerDes, as presented at leading industry conferences, and examine the impact of these advancements on next-generation data centers and AI ecosystems.

Short CV:
Noman Hai (Member, IEEE) earned his B.E. degree in Electrical Engineering from NED University, Karachi, Pakistan, in 2002, followed by M.Sc. in Electrical Engineering from Linköping University, Sweden, in 2006, and Ph.D. in Electrical Engineering from the University of Waterloo, Canada, in 2012. His doctoral research focused on the development of CMOS analog-to-digital converters. He has extensive experience in analog design engineering, having held roles at Philips Semiconductors Eindhoven, MACOM Canada, Movellus Canada, and Synopsys Canada. Across these positions, he contributed to the design of high-speed analog circuits for wireline and Machine Learning applications. Currently, he serves as a Senior Analog Design Manager at Synopsys in Mississauga, Canada, where he leads the design of high-speed interface IP circuits focusing on 224Gb/s SerDes development. His research interests span high-speed I/O circuits, design methodology and automation, and mixed-signal circuit design. He is the holder of three U.S. patents.