Publicado em: 05/09/2012

Prof. Fabrizio Ferrandi do Politecnico di Milano palestra no INF

No dia 06 de setembro, quinta-feira, o professor Fabrizio Ferrandi, do Dipartimento di Elettronica e Informazione (DEI) do Politecnico di Milano, palestra no Instituto de Informática da UFRGS, às 13h30min, no Auditório do prédio 67.

  A visita do professor Ferrandi é promovida pelo PPGC.

Os temas das palestras são:

Talk 1:
“Improving Design Regularity by Targeting Custom Standard-Cell Libraries in the Synaptic EU funded project context”, Fabrizio Ferrandi, Politecnico di Milano

Abstract:
On recent deep sub-micron technologies, process variation can significantly affect the production of digital devices. Besides improving regularity at geometrical level, high-level regularity is becoming very attractive to improve manufacturing and parametric yields. This work presents a design methodology to target custom standard-cell libraries to improve the regularity of the resulting layout. It identifies a set of Boolean functions in the input designs and it aims at identifying the subset of cells that minimizes the area/power overhead.

Talk 2:
Bambu – A Free Source Framework for the High-Level Synthesis of Complex Applications, Fabrizio Ferrandi, Politecnico di Milano

Abstract:
There is a growing consensus among VLSI designers that one of the most effective methods to handle the complexity of today’s system-on-chip designs is to use techniques, such as High-Level Synthesis, that start with an abstract behavioral or algorithmic description of a circuit and automatically synthesize a structural description of a digital circuit that realizes the behavior. In fact, the designer of the applications is usually able to program in a High-Level Language (e.g., C language), but he/she has often a limited experience in hardware design. This talk presents bambu, a tool for the high-level synthesis currently under development at Politecnico di Milano in the context of the PandA framework (http://panda.dei.polimi.it/). It integrates compiler optimizations by interfacing with the GCC compiler and implements a novel memory architecture to synthesize complex C constructs (e.g., function calls, pointers, multi-dimensional arrays, structs, …) without requiring three-states for its implementation. It also integrates floating-point units and thus deals with different data types, generating the proper architectures. Moreover, it is also possible to target both ASIC and FPGA technologies by automatically generating customizable scripts for commercial logic and physical synthesis tools. It is also possible to generate different implementation solutions by trading off latency and resource occupation, to support the hardware/software partitioning on heterogeneous platforms. Finally, thanks to its modular organization, it can be easily extended with new algorithms, architectures or methodologies, targeting different application domains or user’s requirements. Constraints, options and synthesis scripts are easily configurable via XML files and it is also possible to generate test benches for automatically comparing the results with the software counterpart.

Currículo do Professor:
Fabrizio Ferrandi received the PhD degree in information and automation engineering from Politecnico di Milano in 1997. He is currently an Associate Professor at the Dipartimento di Elettronica e Informazione (DEI) of the Politecnico di Milano, Italy. He is member of IEEE, EDAA. He has been and is member of different program committees of EDA conferences (DATE, FPL, CODES/ISSS, ARCS,). He received a best paper award at the EURO-VHDL-96 and DATE-99. He has participated and coordinated a number of European and industrial funded projects. He has been working on innovations in the embedded system design tool chain concerning task parallelisation, partitioning, mapping and synthesis at behavioural and logic level.