Publicado em: 20/08/2024

IEEE CEDA Distinguished Lecturer

Prof. Ricardo Reis é 2024-2025 IEEE CEDA Distinguished Lecturer

IEEE CEDA (Council on Electronic Design Automation) foi selecionado como IEEE CEDA Distinguished Lecturer para o período agosto de 2024 a dezembro de 2025. Foram selecionados 4 palestrantes de várias regiões do mundo, para o período 2024/2025. Os membros do CEDA DL Program podem ser convidados a proferirem palestras em qualquer local do mundo e a IEEE CEDA cobre os gastos de viagem e estadia.

As palestras propostas pelo Prof. Ricardo Reis são:

• Physical Design Automation of Transistor Networks: A way to reduce power consumption is to reduce the number of transistors used to implement a circuit, as leakage power is proportional to the number of transistors. It is shown a physical design approach to reduce the number of transistors needed to perform a task. It is proposed an EDA tool set to automatically generate the physical design of any transistor network. It shows an important reduction on power, improving also reliability. A standard cell library has a limited number of logical functions, and a limited number of sizing. The talk is target in optimization methods to reduce the number of transistors of a circuit. The methods allow the realization of any possible logical function or transistor network. It is included comparisons with solutions using the traditional standard cell methodology.
• Trends on EDA: The design quality of modern chips depends on the quality of the EDA tools used in the design flow. With the evolution of nanotechnologies new EDA tools are needed. Some trends on EDA to cope with the evolution of manufacturing processes will be presented. An important set of EDA tools nowadays are the ones to reduce power consumption at all levels of design abstraction. Power Optimization is fundamental in the IoT world. At logic and physical level, it is needed to reduce the transistor count to reduce leakage power. Also, the use of estimation tools and visualization tools are more and more important in modern design flows.
• Visualization Tools: EDA (electronic design automation) tools paved the way for the integration of billions of components in a single integrated circuit. However, many tools still rely on text interfaces. The use of visualizations tools can help not only to provide a visual output of an EDA tool but also to show how a tool is performing in terms of quality of results. A good graphic output can be useful to improve algorithms or develop new ones. The talk is illustrated with several examples, specially, some placement visualization tools are shown and it is provided a perspective how these visualization tools contributed to the improvement and development of new algorithms developed by our group.

Mais informações em: https://ieee-ceda.org/distinguished-lecturers-program/current-distinguished-lecturers