Publicado em: 18/12/2013

Professor e alunos do PGMicro palestraram na Synopsys USA

O Prof. Ricardo Reis e os alunos de doutorado do PGMicro, Guilherme Flach e Tiago Reimann, realizaram duas palestras no dia 22 de novembro passado, na Synopsys, Sunnyvale, USA.

As palestras foram transmitidas por teleconferência para todos os centros da Synopsys em diversas partes do mundo, tendo uma audiência de cerca de 50 pessoas. E, foram precedidas por uma introdução sobre a pesquisa em EDA na UFRGS.

1- Optimization in Physical Design (apresentada por Ricardo Reis)

Abstract:
Power optimization in NanoCMOS must be observed in all levels of abstraction of the design flow and demands an important effort in optimization. As in NanoCMOS static power consumption is related to the amount of transistors, it is fundamental to change the design approach at physical level. It must be used an approach target to reduce the amount of transistors. The traditional standard cell flow don’t really takes care of power minimization at physical level, because there is a limited number of logical functions in a cell library, as well a limited number of sizing versions. To really obtain an optimization at physical level, it is needed to allow the use of any possible logical function, by also using complex cells (Static CMOS complex gates . SCCG) that are not available in a cell library. To have a “freedom” in the logic design step, it is needed the use of an EDA set of tools to let the automatic design of any transistor network (even with a different number of P and N transistors). This approach can reduce the amount of transistors needed to implement a circuit, reducing the power consumption, mainly the leakage power. The talk presents some examples and comparisons between the standard cell approach and the network of transistors approach. The flexibility of the approach can also let the designers to define layout parameters to cope with problems like tolerance to transient effects, yield improvement, printability and DFM. The designer can also manage the sizing of transistors to reduce power consumption, without compromising the clock frequency. High temperatures can reduce the reliability, so it is also important to reduce power consumption to improve reliability. The talk shows a new approach to reduce the amount of transistors by using complex gates and a new set of EDA tools to generate any transistor network. Some results show an important reduction on power consumption, improving also circuit reliability.

2- Gate Sizing (the tool winner of the ISPD 2013 Contest) (apresentada por Guilherme Flach)

Abstract:
It is presented a fast and effective approach to gate-version selection and Vth assignment. In the proposed flow, first a solution without slew and load violation is generated. Then, a Lagrangian Relaxation method is used to reduce leakage power and achieve timing closure while keeping the circuit with none or few violations. If the set of gate-versions given by Lagrangian Relaxation (LR) produces a circuit with negative slack, a timing recovery method is applied to find near-zero positive slack. The solution without negative slack is finally introduced to a power reduction step. For the ISPD 2012 Contest benchmarks the leakage power of our solutions is, on average, 9.53%