Publicado em: 01/06/2011

Professor Ricardo Reis palestra no FTFC

O professor Ricardo Reis foi convidado para uma palestra no primeiro dia do evento FTFC – Low Voltage Low Power, com o Technical Sponsoring da IEEE Circuits and Systems Society. A 10ª edição do evento foi realizada em Marrakech, no Marrocos. A palestra, com título “Power Reduction by using Transistor Networks”, ocorreu dia 30 de maio.

Abstract:

Static power consumption is a major issue in recent CMOS technologies. As static power is related to the amount of transistors, it becomes necessary to define a new physical design approach by using transistor networks in place of the traditional standard cell approach. The traditional standard cell flow doesn?t really take care of power minimization at physical level, because there is a limited number of logical functions in a cell library, as well a limited number of sizing versions. To really obtain a power optimization at physical level, it is needed to allow the use of any possible logical function, by also using complex gates (Static CMOS complex gates ? SCCG) that are not available in a cell library. To have a “freedom” in the logic design step, it is needed the use of an EDA set of tools to let the automatic design of any transistor network (even with a different number of P and N transistors). This approach can reduce the amount of transistors needed to implement a circuit, reducing the power consumption, mainly the leakage power that is proportional to the number of components (transistors).

It is presented some examples and comparisons between the standard cell approach and the network of transistors approach. The flexibility of the approach can also let the designers to define layout parameters to cope with problems like tolerance to transient effects, yield improvement, printability and DFM. The designer can also manage the sizing of transistors to reduce power consumption, without compromising the clock frequency.

Mais informações em http://davis.isep.fr/ftfc/