Seminário em Micro e Nanoeletrônica no INF

Contato

Publicado em: 23/04/2015

No dia 24/4, sexta-feira o prof. Sergio Bampi, ministrará a palestra CMOS Ultra-Low Power Techniques: Near-Threshold Computing and Approximate, às 13h45min, na sala 104 do prédio de salas de aula do Instituto de Informática – prédio 43425(73). O evento faz parte dos Seminários da disciplina MIC06 – Seminários em Micro e Nanoeletrônica, e é aberto a todos os interessados.

Palestrante: Sergio Bampi

Título: CMOS Ultra-Low Power Techniques: Near-Threshold Computing and Approximate Computing

Abstract:

Near-threshold computing in CMOS is a promising alternative to achieve much higher energy efficiencies for any application which can tolerate very wide voltage-frequency scaling. Internet-of-things systems-on-chip will operate in very different power-performance modes, from sub-MHz to peaks of hundreds of MHz. The nano-power range which is achievable in deca-nanometer CMOS at near-VT requires very specific design and management techniques to be applied in systems-on-chip.

This talk presents the methods we developed to design CMOS circuits for a wide dynamic range of VFS (voltage-frequency scaling), specially for near-threshold operation. A 65nm standard-cell based design methodology specific for near-VT is described. Power and timing variability are characterized, so that variation-aware and yet ultra-low Vdd designs are possible. We present a cell design method to avoid unnecessary upsizing and focus on near- and well above threshold regions of operation, without compromising the design in terms of area and energy. For the study cases of medium complexity notch filter design (24kgates), and an 8051 compatible core (20kgates) we demonstrate 8X to 10X energy/operation savings for applications that tolerate ultra-wide frequency scaling (from few MHz to 1GHz) in their operating modes. The results were obtained using the minimal cycle time achievable at each ultra-low supply voltage supply. The extremely low and highly-variable performance at sub- and near-VT have to be addressed by new design paradigm. In this talk we show the use of logic design of approximate adders to increase the timing performance of a class of digital filter circuits, to enable compensating the performance loss inherent to near-VT operation in CMOS. Our results show that the effort to explore energy savings in low power optimized circuits through the approximate computing approach is validated with energy and worst path delay reductions up to 19.4% and 36.7% respectively, compared to the precise arithmetic implementation, without compromising the filters frequency response. Our approximate adder method enables higher levels of energy efficiency in CMOS VLSI filters.

Short Bio:

Graduated in 1979 (Electronics engineer and B.Sc. in Physics degrees) at UFRGS and received in 1986 the Ph. D. in Electrical Engineering from Stanford University (USA). He worked in MOSFET drain engineering, device reliability, device and process development, in HP advanced MOS facility and at Stanford Univ. Center for Integrated Systems. He was a pos-doc at Stanford University Electrical Engineering (1998-99) working on Ultra-Low Power CMOS circuits with adaptive body biasing and circuit techniques for energy efficiency. He was Technical Director of CEITEC civil association from the start-up of its design activities (2005) up to 2008.He received the Landel Moura award from SBMICRO in 2008 for his contributions to the advancement of microelectronics science and technology in Brazil. Sergio Bampi´s research work is in the field of nano-CMOS integrated circuits design, dedicated architectures for video, low power architectures, RF and analog integrated devices and circuits, modeling and simulation of nano-scale devices. He has published more than 200 papers in international conferences and journals in the field of devices, integrated circuits, dedicated VLSI architectures for video and image coding, and CAD tools for physical design.