Publicado em: 26/04/2010

Vice-Reitor do Karlsruhe Institute of Technology da Alemanha palestra no INF

Na próxima quinta-feira, 29/04, às 14h, no Auditório do Centro de Eventos (Prédio 67) do Instituto de Informática da UFRGS, será realizada a palestra do Prof. Dr. Juergen Becker, Vice-Reitor do Karlsruhe Institute of  Technology, Alemanha.

Titulo: ” Cyber-Physical Multi-Processor Systems on Chip – Adaptive Multi-Core Architectures in the Nano Era”.

Abstract:

The field of embedded electronic systems, nowadays also called cyper-physical systems, is still emerging. A cyber-physical system (CPS) is a system featuring a tight combination of, and coordination between, the system’s computational and physical elements. Today, a pre-cursor generation of cyber-physical systems can be found in areas as diverse as aerospace, automotive, chemical processes, civil infrastructure, energy, healthcare, manufacturing, transportation, entertainment, and consumer appliances. This generation is often referred to as embedded systems. In embedded systems the emphasis tends to be more on the computational elements, and less on an intense link between the computational and physical elements.

Multipurpose adaptivity and reliability features are playing more and more of a central role, especially while scaling silicon technologies down according to Moore´s benchmarks. Leading processor and mainframe companies are gaining more awareness of reconfigurable computing technologies due to increasing energy and cost constraints. My view is of an “all-win-symbiosis” of future silicon-based processor technologies and reconfigurable circuits/architectures. Dynamic and partial reconfiguration has progressed from academic labs to industry research and development groups, providing high adaptivity for a range of applications and situations. Reliability, failure-redundancy and run-time adaptivity using real-time hardware reconfiguration are important aspects for current and future systems. Thus, scalability, as we have experienced for the last 35 years is at its end as we enter the so-called Nano Era. Beyond the capabilities of traditional reconfigurable fabrics (like FPGAs), nano circuits/architectures allow for micro-mechanical switches that enable new memory and reconfiguration technologies with the advantage of online chip adaptivity and non-volatility. Transient faults may lead to unreliable information processing as information in nano-sized devices is much less. Power consumption and related problems present a challenge where information is processed within a smaller area/volume budget. This includes the consideration of appropriate fault tolerance techniques and especially the discussion of necessary efficient and online self-repairing mechanisms for driving such kind of future technologies and architectures.

This keynote will finally discuss in detail the corresponding challenges and specifically outline the promising perspectives for future multi-core as well as dynamically reconfigurable, complex, adaptive and reliable systems-on-chip, for embedded and also general purpose computing systems.

Short CV:
Jürgen Becker is Full Professor for Embedded Electronic Systems in the department of Electrical Engineering and Information Technology at Universität Karlsruhe (TH). His actual research is focused on industrial-driven System-on-Chip (SoC) integration with emphasis on adaptivity, e.g. dynamically reconfigurable hardware architecture development and application in automotive and communication systems. Prof. Becker is Head of the Institute for Information Processing (ITIV) and Department Director of Electronic Systems and Microsystems (ESM) at the Computer Science Research Center (FZI). From 2001- 2005 he has been Co-Director of the International Department at Universität Karlsruhe (TH). He is author and co-author of more than 250 scientific papers, and active as general and technical program chairman of national / international conferences and workshops. He is executive board member of the german IEEE section, Board member of the GI/ITG Technical Committee of Architectures for VLSI Circuits, Associate Editor of the IEEE Transactions on Computers, and Senior Member of the IEEE. Since October 2005 Prof. Becker is Vice-President (“Prorektor”) for Studies and Teaching at Universität Karlsruhe (TH), which is currently emerging into the new Karlsruhe Institute of Technology – KIT – the consequent and unique merger of a large national research lab in the Helmholtz Society as well as of a prominent state university of Baden-Wuerttemberg in Germany.

Vice-Reitor do Karlsruhe Institute of  Technology da Alemanha palestra no INF

Na próxima quinta-feira, 29/04, às 14h, no Auditório do Centro de Eventos (Prédio 67) do Instituto de Informática da UFRGS, será realizada a palestra do Prof. Dr. Juergen Becker, Vice-Reitor do Karlsruhe Institute of  Technology, Alemanha.

Titulo: " Cyber-Physical Multi-Processor Systems on Chip - Adaptive Multi-Core Architectures in the Nano Era".

Abstract:

The field of embedded electronic systems, nowadays also called cyper-physical systems, is still emerging. A cyber-physical system (CPS) is a system featuring a tight combination of, and coordination between, the system’s computational and physical elements. Today, a pre-cursor generation of cyber-physical systems can be found in areas as diverse as aerospace, automotive, chemical processes, civil infrastructure, energy, healthcare, manufacturing, transportation, entertainment, and consumer appliances. This generation is often referred to as embedded systems. In embedded systems the emphasis tends to be more on the computational elements, and less on an intense link between the computational and physical elements.

Multipurpose adaptivity and reliability features are playing more and more of a central role, especially while scaling silicon technologies down according to Moore´s benchmarks. Leading processor and mainframe companies are gaining more awareness of reconfigurable computing technologies due to increasing energy and cost constraints. My view is of an “all-win-symbiosis” of future silicon-based processor technologies and reconfigurable circuits/architectures. Dynamic and partial reconfiguration has progressed from academic labs to industry research and development groups, providing high adaptivity for a range of applications and situations. Reliability, failure-redundancy and run-time adaptivity using real-time hardware reconfiguration are important aspects for current and future systems. Thus, scalability, as we have experienced for the last 35 years is at its end as we enter the so-called Nano Era. Beyond the capabilities of traditional reconfigurable fabrics (like FPGAs), nano circuits/architectures allow for micro-mechanical switches that enable new memory and reconfiguration technologies with the advantage of online chip adaptivity and non-volatility. Transient faults may lead to unreliable information processing as information in nano-sized devices is much less. Power consumption and related problems present a challenge where information is processed within a smaller area/volume budget. This includes the consideration of appropriate fault tolerance techniques and especially the discussion of necessary efficient and online self-repairing mechanisms for driving such kind of future technologies and architectures.

This keynote will finally discuss in detail the corresponding challenges and specifically outline the promising perspectives for future multi-core as well as dynamically reconfigurable, complex, adaptive and reliable systems-on-chip, for embedded and also general purpose computing systems.

Short CV:

Jürgen Becker is Full Professor for Embedded Electronic Systems in the department of Electrical Engineering and Information Technology at Universität Karlsruhe (TH). His actual research is focused on industrial-driven System-on-Chip (SoC) integration with emphasis on adaptivity, e.g. dynamically reconfigurable hardware architecture development and application in automotive and communication systems. Prof. Becker is Head of the Institute for Information Processing (ITIV) and Department Director of Electronic Systems and Microsystems (ESM) at the Computer Science Research Center (FZI). From 2001- 2005 he has been Co-Director of the International Department at Universität Karlsruhe (TH). He is author and co-author of more than 250 scientific papers, and active as general and technical program chairman of national / international conferences and workshops. He is executive board member of the german IEEE section, Board member of the GI/ITG Technical Committee of Architectures for VLSI Circuits, Associate Editor of the IEEE Transactions on Computers, and Senior Member of the IEEE. Since October 2005 Prof. Becker is Vice-President ("Prorektor") for Studies and Teaching at Universität Karlsruhe (TH), which is currently emerging into the new Karlsruhe Institute of Technology – KIT – the consequent and unique merger of a large national research lab in the Helmholtz Society as well as of a prominent state university of Baden-Wuerttemberg in Germany.