RICARDO REIS

PROFESSOR

ACTIVITIES (BRAZILIAN)

Ensino

- Professor do Curso de Decodificação e Teste de Circuitos Integrados, 6 ème Ecole d'ete du Forez (Projeto de C.I.), de 23 de agosto de 1981 a 6 de setembro de 1981, em Vendes, Cantal, França.

- Palestrante convidado, da Universidade de Karlsruhe, Alemanha Ocidental, de 31 de janeiro a 4 de fevereiro de 1983.

- Professor do Curso “Taller de Concepción de Circuitos Integrados”, Facultad de Ciencias de la universidad de Valparaíso, de 9 a 14 de fevereiro de 1997.

- Professor das I Jornadas IberoAmericanas de Diseno Digital a Alto Nível, Curso de Síntese Física, Cartagena, Colombia, 25 a 29 de setembro, 2000. Promoção CYTED -AECI.

Pesquisa

- Missão de trabalho CAPES/COFECUB Brasil/França, junto ao Institut National Polytechnique de Grenoble, dez/89 e jan/90.

- Missão de trabalho CAPES/Bélgica, junto a Université Catholique de Louvain-la-Neuve, fevereiro de 1990.

- Coordenador Nacional do Projeto Multiusuário Ibero-Americano, integrante do Programa CYTED-D, liderado pela Espanha, 1990/1994.

- Missão CAPES/COFECUB Brasil/França, junto ao Institut National Polytechnique de Grenoble e a Universidade de Montpellier II, setembro 93.

- Projeto ILA9200- Microprocessador Didático, em conjunto com Espanha, México, Argentina e Colômbia, no contexto do Projeto PMU- CYTED-D.

- Membro do Programa CHIPSHOP (Programa ESPRIT da CEE) para o Brasil.

- Coordenador do Projeto CAPES/COFECUB (Brasil/França) 135/93 "Concepção Automática de Circuitos Integrados", 1993/1997.

- Coordenador na UFRGS do Projeto ALFA tipo B1-(Preliminary Activities to the Mobility) envolvendo França, Alemanha, Bélgica, Portugal,México, Colômbia e Brasil. Titulo:"Design, Synthesis and Test of Digital Systems", 1998.

- Coordenador na UFRGS do Projeto ALFA tipo B2- (Devising Common Research Projects), envolvendo França, Alemanha, Bélgica, Portugal,México, Colômbia e Brasil. Titulo: "Synthesis of Testable Circuits and Systems", 1998.

- Coordenador do Projeto CAPES/COFECUB (Brasil/França) nº 245/98-I "CAD de Sistemas e de Circuitos Integrados Digitais", 1998/2000.

- Coordenador do Projeto CNPq/DLR (Brasil/Alemanha) “DInCAD: Distributed Internet-based CAD Methods for Future Complex Microelectronic Systems”, UFRGS/Darmstadt, 1999-2003

- Coordenador do Projeto CNPq/CSIC (Brasil/Espanha), processo nº 910106/98-3 “Verificação e Teste de Circuitos Integrados Mistos e Microssistemas” 2001/2002.

- Coordenador do Projeto CAPES/COFECUB (Brasil/França) nº 373/01 "Concepção de Arquiteturas Multiprocessadores Mistas Hardware/Software", 2001/2004.

- Coordenador do Projeto CAPES/ICCTI (Brasil/Portugal) nº 086/02 " Síntese Automática de Circuitos Integrados Visando Alto Desempenho e Baixo Consumo ", 2002/2005.

- Coordenador do Projeto CAPES/MECD (Brasil/Espanha) nº 051/03 “Síntese e Verificação de Circuitos Integrados Digitais CMOS de Alto Desempenho” , 2003/2004

- Coordenador na UFRGS do Projeto ALFA NICRON - Fault-Tolerant System Design and Verification for Safety-Critical Applications Built from Advanced Integrated Circuits, envolvendo França, Itália, Espanha, Portugal, México, Colômbia, Uruguai, Argentina e Brasil. 2006/2008.

Organização de Eventos

- VLSI’97 IX IFIP International Conference on VLSI, Gramado, 26 a 30 Agosto 1997

- IFIP Working Group 10.5 Meeting, Gramado, 29 de Agosto de 1997.

- IFIP Technical Committee 10 Meeting, Gramado, 30 e 31 de Agosto de 1997.

- Assembléia Geral da IFIP (International Federation on Information Processing), Canela, Brasil, de 1 a 5 de setembro de 1997.

- Seminário do Programa ALFA B2- Synthesis of Testable Circuits and Systems, Garopaba, de 15 a 19 de fevereiro, 1998.

- VLSI’99, X IFIP International Conference on Very Large Scale Integration, Lisboa, 1 a 4 de dezembro de 1999 ( Publications Chair)

- IFIP Technical Committee 10 Meeting, Pirenópolis, 10 de setembro de 2001.

- IFIP IT Conference, Natal, 31 de Agosto e 1 de setembro de 2001.

- Assembléia Geral da IFIP (International Federation on Information Processing), Natal, Brasil, de 1 a 5 de setembro de 2001.

- VLSISoC2003, XII IFIP International Conference on Very Large Scale Integration, Darmstadt, Alemanha, 1 a 3 de dezembro de 2003 ( Publications Chair)

- Chair of the Steering Committee of IFIP VLSI-SoC Series of Conferences.

- VLSISoC2005, XIII IFIP International Conference on Very Large Scale Integration, Perth, Australia, 17 a 19 de Outubro de 2005 ( Publications Chair)

- IEEE CS ISVLSI 2007, IEEE Computer Society Annual Symposium on VLSI, Porto Alegre, Brazil, May 9-11, 2007, como General Chair.

- IBERCHIP 2010, 16th Workshop IBERCHIP, Iguaçu Falls, Brazil, February 23-25, 2010, como General Chair.

- LASCAS 2010. First IEEE Latin American Symposium on Circuits and Systems, Iguaçu Falls, February 24-26, 2010, como General Chair.

Comitê de Programa de Eventos

- PATMOS'94 - Fourth International Workshop on Power and Timing Modeling, Optimization and Simulation, October 17-19, 1994, Barcelona, Espanha.

- PATMOS'95- Fith International Workshop on Power and Timing Modeling, Optimization and Simulation, October 4-6,1995, Oldenburg, Alemanha.

- ICCDCS-95, IEEE International Caracas Conference on Devices, Circuits and Systems, December 12-14, 1995, Caracas, Venezuela.

- PATMOS'96 - Sith International Workshop on Power and Timing Modeling, Optimization and Simulation, September 23-25, 1996, Bologna, Itália.

- PATMOS'97 - Seven International Workshop on Power and Timing Modeling, Optimization and Simulation, September 8-10, 1997, Louvain-la-Neuve, Belgica.

- VLSI’97 IX IFIP International Conference on VLSI, Gramado, 26 a 30 Agosto 1997

- PATMOS'98 - Eight International Workshop on Power and Timing Modeling, Optimization and Simulation, October 7-8, 1998, Lyngby, Dinamarca.

- PATMOS'99 - Ninth International Workshop on Power and Timing Modeling, Optimization and Simulation, October 6-9, 1999, Kos, Grécia.

- VLSI’99, X IFIP International Conference on Very Large Scale Integration, Lisboa, 1 a 4 de dezembro de 1999.

- PATMOS'00 - Tenth International Workshop on Power and Timing Modeling, Optimization and Simulation, September 13-15, 2000, Goettingen, Alemanha.

- PATMOS'01 – 11th International Workshop on Power and Timing Modeling, Optimization and Simulation, September 26-28, 2001, Yverdon, Switzerland.

- VLSI-SoC’01, XI IFIP International Conference on Very Large Scale Integration, Montpellier, December 3–5, 2001.

- PATMOS’02 - 12th International Workshop on Power and Timing Modeling, Optimization and Simulation, Sevilha, Espanha, September 11-13, 2002

- PATMOS’03 - 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, Torino, September 10-12, 2003.

- VLSI-SoC’03, XII IFIP International Conference on Very Large Scale Integration, Darmstadt, December 1–3, 2003.

- IEEE/ACM/IFIP CODES+ISSS 2003, International Conference on Hardware/Software Codesign and System Synthesis, Newport Beach, October 1-3, 2003.

- IFIP WCC2004- World Computer Congress, Toulouse, França, 22 a 27 de Agosto de 2004.

- IFIP EDUTECH 2004, Toulouse, França, 26 a 27 de Agosto de 2004

- IEEE/ACM/IFIP CODES+ISSS 2004, International Conference on Hardware/Software Codesign and System Synthesis, Stockholm, Sweden, September 8-10, 2004.

- PATMOS’04 - 14th International Workshop on Power and Timing Modeling, Optimization and Simulation, Santorini, Grecia, September 15-17, 2004.

- IEEE CS RAW 2005, 12th Reconfigurable Architectures Workshop, April 4 - 5, 2005, Denver, Colorado, USA

- PATMOS’05 - 15th International Workshop on Power and Timing Modeling, Optimization and Simulation, Leuven, Belgium, September 20-23, 2005.

- IEEE/ACM/IFIP CODES+ISSS 2005, International Conference on Hardware/Software Codesign and System Synthesis, New York, USA, September 18-21, 2005.

- IFIP EDUTECH 2005, Perth, Australia, 20 a 21 de October de 2005

- IEEE CS ISVLSI 2006, IEEE Computer Society Annual Symposium on VLSI, Karlsruhe, Germany, March 2-3, 2006

- IEEE CS RAW 2006, 13th Reconfigurable Architectures Workshop, April 25 – 26, 2006, Rhodes Island, Greece

- IFIP BICC - IFIP Conference on Biologically Inspired Cooperative Computing, August 20-25, Santiago, Chile, 2006.

- PATMOS’06 - 16th International Workshop on Power and Timing Modeling, Optimization and Simulation, Montpellier, France, September 13-15, 2006.

- IEEE ICECS – 13th IEEE International Conference on Electronics, Circuits and Systems, Nice, France, December 10-13, 2006

- IEEE LATW 2007 – 8th Latin American Test Workshop, Cusco, Peru, March 11-14, 2007.

- IEEE CS RAW 2007, 14th Reconfigurable Architectures Workshop, March 26-27, 2007, Long Beach, California, USA

- IEEE CS ISVLSI 2007, IEEE Computer Society Annual Symposium on VLSI, Porto Alegre, Brazil, May 9-11, 2007

- RC Education 2007- The 2nd International Workshop on Reconfigurable Computing Education, May 12, 2007, Porto Alegre, Brazil

- PATMOS’07 - 17th International Workshop on Power and Timing Modeling, Optimization and Simulation, Göteborg, Sweden, September 3-5, 2007.

- VLSI-SoC 2007 – 15th IFIP/IEEE International Conference on Very Large Scale Integration, October 15-17, Atlanta, USA.

- IEEE ICECS – 14th IEEE International Conference on Electronics, Circuits and Systems, Marrakesh, Marrocos, December 11-14, 2007

- IEEE CS ISVLSI 2008, IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, April 7-9, 2008

- RC Education 2008 - The 3rd International Workshop on Reconfigurable Computing Education, April 10, 2008, Montpellier, France.

- IEEE CS RAW 2008, 15th Reconfigurable Architectures Workshop, April 14-15, 2008, Miami, Florida, USA

- IFIP BICC - 2nd IFIP Conference on Biologically Inspired Cooperative Computing, September 7-10, Milano, Italy, 2008.

- IEEE ICECS – 15th IEEE International Conference on Electronics, Circuits and Systems, Malta, August 31 - September 3, 2008

- PATMOS’08 - 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, Lisbon, Portugal, September 10-12, 2008.

- VLSI-SoC 2008 – 16th IFIP/IEEE International Conference on Very Large Scale Integration, October 13-15, Rhodes, Greece.

- ANDESCON 2008, Cusco, Peru, October 15-17, 2008.

- ReConFig'08- 2008 International Conference on ReConFigurable Computing and FPGAs, December 3-5, 2008, Cancun, Mexico

- PATMOS 2009, 19th International Workshop on Power And Timing Modeling, Optimization and Simulation, September 9-11, 2009, Delft, The Netherlands.

- ReCoSoc 2010

- ISVLSI 2010, IEEE Computer Society Annual Symposium on VLSI, July 2010, Kefalonia, Greece.

- PATMOS 2010, Grenoble, France.

- VLSISoC 2010

Participação em Feiras Internacionais

- 36th IEEE/ACM Design Automation Conference, New Orleans, June 21-24, 1999. Com a demonstração dos seguintes trabalhos:

- CAVE-WWW Based Design Automation Framework

- TROPIC3 - a fast automatic layout generator for CMOS digital circuits

- Maragata - Designing Circuits with Programmable Universal Logic Gates

- 37th IEEE/ACM Design Automation Conference, Los Angeles, June 5-8, 2000. Com a demonstração dos seguintes trabalhos:

- CAVE2 - WWW Based Design Automation Framework

- WTROPIC - A WWW-Based Macro Cell Generator

- 38th IEEE/ACM Design Automation Conference, Las Vegas, June 18-22, 2001. Com a demonstração dos seguintes trabalhos:

- New Algorithms for VLSI Routing

- Cooperative work in CAVE Framework

- 39th IEEE/ACM Design Automation Conference, New Orleans, June 10-14, 2002. Com a demonstração dos seguintes trabalhos:

- Lemon Dragon

- Cooperative work in CAVE Framework

- 40th IEEE/ACM Design Automation Conference, Anaheim, June 2-6, 2003. Com a demonstração dos seguintes trabalhos:

- Parrot

- Tic-Tac: Timing Analysis Tool

- 41th IEEE/ACM Design Automation Conference, San Diego, June, 2004. Com a demonstração dos seguintes trabalhos:

- Síntese Física Automática

- 42th IEEE/ACM Design Automation Conference, Anaheim, June 13-16, 2005. Com a demonstração dos seguintes trabalhos:

- Processamento Paralelo de Ferramentas de CAD, demonstrando a paralelização de ferramentas de Posicionamento.

- 43th IEEE/ACM Design Automation Conference, San Francisco, USA, July 24-27, 2006. Com a demonstração do seguinte trabalho:

- Ferramentas de CAD para o posicionamento de células em circuitos 3D.

- 44th IEEE/ACM Design Automation Conference, San Diego, USA, June 4-8, 2007. Com a demonstração do seguinte trabalho:

- Ferramentas de CAD para a síntese fisica automática de células.

- 45th IEEE/ACM Design Automation Conference, Anaheim, USA, June 8-13, 2008. Com a demonstração do seguinte trabalho:

- ICPD: A Graphical CAD Framework for Physical Synthesis

- 46th IEEE/ACM Design Automation Conference, San Francisco, USA, July 2009.

- 47th IEEE/ACM Design Automation Conference, Anaheim USA, June 2009.

Administrativo

- Membro do Comitê de Marketing da IFIP ( International Federation for Information Processing).

- Membro da Assembléia Geral da IFIP, representando a SBC, desde outubro de 1994.

- Membro do Conselho da IFIP, 1996 a 1999 e de 1999 a 2000, de 2005 a ...

- Vice-Presidente da IFIP de 2000 a 2001.

- Vice-presidente da IFIP de 2001 a 2004

- Vice-presidente da IEEE Circuits and Systems Society, 2008 a 2011.