PHD THESIS

20- Guilherme Augusto Flach, “Discrete Gate Sizing and Timing-Driven Detailed Placement for the Design of Digital Circuits”, December 20, 2015, PGMicro/UFRGS. As co-advisor.

19- Jorge Lucio Tonfat Seclen, "Frame-Level Redundancy Scrubbing Technique for SRAM-based FPGAs", August 4, 2015, PGMicro/UFRGS.

18- Gracieli Posser, " Electromigration Aware Cell Design ", March 2, 2015, PPGC/UFRGS

17- Cristina Meinhard, " Variabilidade em FinFETs ", December 19, 2014, PPGC/UFRGS.

16- Cristiano Lopes dos Santos, "Heat Dissipation and Thermal Analysis for 3D ICs", November 20, 2014, PGMicro/UFRGS.

15- Adriel Ziesemer, “Síntese Automática do Leiaute de Redes de Transistores”, May 5, 2014, PGMicro/UFRGS.

14- Sidinei Ghissoni, “Decomposição de Coeficientes Trigonométricos para a Redução de Área e Potência em Arquiteturas FFT Híbridas na Base 2”, December 19, 2012, PGMicro/UFRGS.

13- Rodrigo Possamai Bastos, “Transient-Fault Robust Systems Exploiting Quasi-Delay Insensitive Asynchronous Circuits”, July 30, 2010, PGMicro/UFRGS. Co-Advisor: Fernanda Kastensmidt in co-tutelle with INPG, France.

12- Sandro Sawicki, “Particionamento de Células e Pads de I/O em Circuitos VLSI 3D”, November 30, 2009, PPGC/UFRGS.

11- Gustavo Reis Wilke, “Analysis and Optimization of Mesh-based Clock Distribution Architectures”, September 1, 2008, PGMicro/UFRGS.

10- Cristiano Lazzari, “Transistor Level Automatic Generation of Radiation-Hardened Circuits”, December 3, 2007, PGMicro/UFRGS.

9- José Carlos Sant'Anna Palma, “Reduzindo o Consumo de Potência em Networks-on-Chip através de Esquemas de Codificação de Dados”, September 3, 2007, PPGC/UFRGS.

8- Gustavo Neuberger, “Protecting Digital Circuits against Hold Time Violations Due to Process Variations”, September 3, 2007, PGMicro/UFRGS.

7- Lisane Brisolara de Brisolara, “Strategies for Embedded Software Development based on High-level Models”, August 31, 2007, PPGC/UFRGS.

6- Renato Fernandes Hentschke, “Algorithms for Wire Length Improvement of VLSI Circuits With Concern to Critical Paths”, June 8, 2007, PPGC/UFRGS.

5- Fernanda Gusmão de Lima Kastensmidt, " Designing Single Event Upset Mitigation Techniques for Large SRAM-Based FPGA Components", September 2003, PPGC/UFRGS.

4- Leandro Soares Indrusiak, " A Framework Supporting Collaboration on the Distributed Design of Integrated Systems", September 2003, PPGC/UFRGS.

3- João Baptista dos Santos Martins, “Estimativa de Capacitâncias e Consumo de Potência em Circuitos Combinacionais CMOS no Nivel Lógico”, July 2001, PPGC/UFRGS.

2- Marcelo de Oliveira Johann, "Novos Algoritmos para o Roteamento de Circuitos VLSI.", April 2001, PPGC/UFRGS.

1- José Luís A. Güntzel, "Análise de Timing Funcional de Circuitos VLSI Contendo Portas Complexas", November 2000, PPGC/UFRGS.