INTERNACIONAL CONFERENCES

1. REIS, Ricardo Augusto da Luz. Tess; a Topological Evaluator Tool. In: IEEE INTERNATIONAL CONFERENCE ON CIRCUITS AND COMPUTERS, New York, Sept. 28 - Oct. 1, 1982. Proceedings. New York, IEEE, 1982.

2. REIS, Ricardo Augusto da Luz. A Topological Evaluator as The First Slep in VlSI Design. In: MICROELECTRONICS, Adelaide, May 12-14, 1982. Proceedings. Austrália, Institute of Engineers, 1982. p. 22.

3. REIS, Ricardo Augusto da Luz. Avaliação Topológica de Circuitos VLSI (trabalho convidado). In: JORNADAS DE DISENO LÓGICO, 2., Barcelona, dez. 14-16, 1983. Anais. Barcelona, Universidad Autonoma de Barcelona, 1983.

4. REIS, Ricardo Augusto da Luz. TESS: a Topological Evaluator Tool for VLSI Circuits. In: INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS, Taipei, March 30 - Apr. 1, 1983. Proceedings.

5. REIS, Ricardo Augusto da Luz; JERRAYA, A.; JAMIER, R. A Microprocessor Design Using the Syco Compiler. In: WORKSHOP ON ARCHITECTURAL SYNTHESIS OF DIGITAL SYSTEMS, Torino, May 22-23, 1986. Proceedings. IFIP, 1986.

6. REIS, Ricardo Augusto da Luz; JERRAYA, A.; JAMIER, R. Design of the Syco 6502 Using the Syco Compiler. In: ICCD 86 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, New York, Oct. 6-9, 1986. Proceedings. New York, IEEE, 1986. p. 68-71

7. REIS, Ricardo Augusto da Luz. A New Standard Cell CAD Methodology. In: IEEE Custom Integrated Circuits Conference, Portland, Oregon, May 4-7, 1987. Proceedings, New York, IEEE, 1987. p. 385-388.

8. REIS; Ricardo Augusto da Luz; GOMES, Rogério Figurelli; LUBASZEWSKI, Marcelo. An Efficient Design Methodology for Standard Cell Circuits. In: IEEE INTERNATIONAL SYMPOSIUM on CIRCUITS and SYSTEMS, Espoo, Jun. 7-9, 1988. Proceedings. New York: IEEE, 1988. V.2 p. 1213-16.

9. BAMPI, Sérgio; REIS, Ricardo Augusto da Luz. Education and Research Profile of the Microelectronics Group at CPGCC-UFRGS In: COLLOQUE FRANCO-BRESILIEN EN CONCEPTION ASIC., Paris, 13-17 Abril 1992.Anais. Paris: Universidade de Paris VI, 1992. p. 8-11.

10. REIS, Ricardo. ASIC Synthesis from High Level Specification. (Artigo Convidado). In: ISIE 94 - IEEE International Symposium on Industrial Electronics, Santiago, Chile, 25-27 Maio 1994.

11. MAHLMANN, Luiz; KINDEL, Marcus; REIS, Ricardo.TENTOS for WINDOWS: Ferramentas para Projeto Fisico de CI's. In: Primer Workshop IBERCHIP, Cartagena, Colombia, 6-10 Fevereiro 1995. p.357-366.

12. GÜNTZEL, José; REIS, Ricardo; FLORES, Aline ; FREITAS, Demétrio. A Sea-of-Cells Approach for ASIC Design. In: Primer Workshop IBERCHIP, Cartagena, Colombia, 6-10 Fevereiro 1995. p.281-290.

13. GÜNTZEL, José; REIS, Ricardo. ASIC Design Using a Sea-of-Cells Approach. In: EDAC 95 - European Design and Test Conference, User Forum, IEEE Computer Society, Paris, 6-9 Março 1995, p. 255.

14. JOHANN, Marcelo; KINDEL, Marcus; REIS, Ricardo. Layout Synthesis Using Transparent Cells and FOTC Routing. 38th IEEE Midwest Symposium on Circuits and Systems, IEEE Circuits and Systems Society, Rio de Janeiro, 13-16 Agosto 1995.

15. GUNTZEL, José; REIS, Ricardo FLORES, Aline; JOHANN, Marcelo. A Novel Approach for ASIC Layout Generation. 38th IEEE Midwest Symposium on Circuits and Systems, IEEE Circuits and Systems Society, Rio de Janeiro, 13-16 Agosto 1995. Proceedings. Vol2. p.791-794.

16. JOHANN, Marcelo; REIS, Ricardo. A Full Over-the-Cell Routing Model. In: IFIP VLSI 95, IFIP/IEEE/ACM, Tokyo, 26 Agosto-1 Setembro 1995, p. 845-850.

17. REIS, A.; ROBERT, M.; AUVERGNE, D.; REIS, R.. From TBDDs Functional Representations to CMOS Complex Gates. X System and Integrated Circuits Design Congress (SICD), Zaragoza, Espanha, 15-17 Novembro 1995, p. 159-164.

18. MORAES, F.; REIS, A.; ROBERT, M.; AUVERGNE, D.; REIS, R.. Library Free Implementation of CMOS digital ASICs. X System and Integrated Circuits Design Congress (SICD), Zaragoza, Espanha, 15-17 Novembro 1995, p. 191-196.

19. CARRO, L.; MORAES, F.; JOHANN, M.; KINDEL, M.; BENONI, P.; MIGLIORIN, G.; REIS, R.; SUZIM, A. An Environmenet to Design Digital Circuits Based on the Brazilian Gate-Array. In: Segundo Workshop IBERCHIP, São Paulo, 12-15 Fevereiro 1996. p.198-205.

20. MORAES, F.; REIS, R.; TORRES, L.; ROBERT, M.; AUVERGNE, D., Pre-Layout Performance Prediction for Automatic Macro-Cell Synthesis In: IEEE INTERNATIONAL SYMPOSIUM on CIRCUITS and SYSTEMS, Atlanta, 12-15 de Maio 1996. Proceedings. New York: IEEE, 1996.

21. REIS, André; REIS, Ricardo.; ROBERT, Michel; AUVERGNE, Daniel; Assignement Technologique sur Portes Complexes. In: Colloque CAO de Circuits Intégrés et Systèmes, Villard de Lans, França, 15-17 Janeiro 1997. pp. 291-294.

22. MAHLMANN, L.G. ;MORAES. F.; GUNTZEL, J.; REIS, R.; Tentos for Windows - Um Sistema para Microeletrônica In: Tercer Workshop IBERCHIP, México, 19-21 Fevereiro 1997. p.513-522.

23. CARRO, L.; JOHANN, M.; KINDEL, M.; GONÇALVES, P.; LIMA, A.; MIGLIORIN, G.; NARDI, G.; MORAES. F.; REIS, R.; JACOBI, R.; SUZIM, A. Ambiente ÁGATA de Projeto Versão Beta 2.0 In: Tercer Workshop IBERCHIP, México, 19-21 Fevereiro 1997. p.494-503.

24. FRAGOSO, J.; GUNTZEL, J.; REIS, R.; An X-Windows/Motif Interface for Fast Prototyping using Marcela Prediffused Masterslices In: Tercer Workshop IBERCHIP, México, 19-21 Fevereiro 1997. p.504-509.

25. REIS, André; REIS, Ricardo.; ROBERT, Michel; AUVERGNE, Daniel. The Library Free Technology Mapping Problem. In: IEEE/ACM International Workshop on Logic Synthesis 97, IEEE, Lake Tahoe, USA, 18 a 21 Maio de 1997.

26. INDRUSIAK, Leandro; REIS, Ricardo. Microelectronics Learning Using WWW and VRML. In: IFIP 9.4 International Conference: Information Technology for Competitiveness. Florianópolis, 19 a 21 de junho de 1997.

27. GÜNTZEL, José L.; PINTO, Ana Cristina M.; REIS, Ricardo A. L. Improving Path Enumeration Accuracy by Considering Different Fall and Rise Gate Delays. In: QUARTO WORKSHOP IBERCHIP, Mar del Plata (Argentina), March 11-13, 1998. p. 91-100.

28. LIMA, Fernanda G..; GÜNTZEL, José L.; JOHANN, Marcelo de O.; CARRO, Luigi; REIS, Ricardo A. L. On The Applicability of Universal Logic Gates for Designing Masked Programmable Gate Array Architectures. In: QUARTO WORKSHOP IBERCHIP, Mar del Plata (Argentina), March 11-13, 1998. p. 110-119.

29. INDRUSIAK, Leandro; REIS, Ricardo. 3D Integrated Circuit Layout Visualization using VRML, In: SCS WEBSIM99 – International Conference on Web-Based Modelling and Simulation, San Francisco, USA, January 17-21, SCS Simulation Series Vol. 31 Number 3, 1999, p. 177-181.

30. LIMA, Fernanda G.; GÜNTZEL, José L.; JOHANN, Marcelo de O.; CARRO, Luigi; REIS, Ricardo A. L. Designing Masked Programmable ULGs for MPGAs. In: QUINTO WORKSHOP IBERCHIP, Lima (Peru), March 1-3, 1999. p. 91-99.

31. GÜNTZEL, José L.; PINTO, Ana; FRAGOSO, João; DALL PIZZOL, Guilherme; REIS, Ricardo A. L. Path Enumaration Algorithms for Timing Analysis of Digital Circuits. In: QUINTO WORKSHOP IBERCHIP, Lima (Peru), March 1-3, 1999. p. 334-341.

32. FRAGOSO, João; REIS, Ricardo A. L. Um Divisor Polinomial Parametrizavel em VHDL. In: QUINTO WORKSHOP IBERCHIP, Lima (Peru), March 1-3, 1999. p. 308-314.

33. REIS, André; ROBERT, Michel; REIS, Ricardo. TABA: A Tool for Library Free Technology Mapping. In: QUINTO WORKSHOP IBERCHIP, Lima (Peru), March 1-3, 1999. p. 238-246.

34. COSTA, E; FERREIRA, F.; LIMA, F.; FRAGOSO, J.; BUSS, M.; BARCELOS, M.; SANTOS, R.; SERRA, T; ROCHOL, J.; BAMPI, S.; REIS, R. LAWAI: Uma Alternativa para a Interligação de LAN's a Grande Distância. In: QUINTO WORKSHOP IBERCHIP, Lima (Peru), March 1-3, 1999. p. 325-333.

35. INDRUSIAK, L.S.; REIS, R.A.L.; BECKER, J.; GLESNER, M. DInCAD: Distributed Internet-based CAD Methods for Future Complex Microelectronic Systems, V Workshop of the German-Brazilian Bilateral Programme for Scientific and Technological Cooperation through BMBF / CNPq, Koenigswinter, Alemanha, March 1-3, 1999.

36. REIS, André; ROBERT, Michel; REIS, Ricardo Covering Strategies for Library Free Technology Mapping, International Workshop on Logic Synthesis 1999 (IWLS99), June 1999, pg. 50-59.

37. REIS, Ricardo; INDRUSIAK, Leandro. Microelectronics Education Using WWW. In: IEEE Microelectronics System Education, Arlington, USA, July 19-21. Anais. IEEE Computer Society, 1999, pg. 43-44.

38. REIS, Ricardo; INDRUSIAK, Leandro. VRML and Microelectronics Education. In: IEEE Microelectronics System Education, Arlington, USA, July 19-21. Anais. IEEE Computer Society, 1999, pg. 84-85.

39. INDRUSIAK, Leandro; REIS, Ricardo. Project Management and Design Methodology Support for the CAVE Project: A Hyperdocument-Centric Approach In: Symposium on Integrated Circuits and Systems Design, 12, Natal, RN, 28 setembro a 2 outubro 1999. Anais. IEEE Computer Society, 1999. pg.188-191. ISBN 0-7695-0387-X

40. FRAGOSO, J.; COSTA, E; ROCHOL, J.; BAMPI, S.; REIS, R. Specification and Design of an Ethernet Interface Soft IP, In: Symposium on Integrated Circuits and Systems Design, 12, Natal, RN, 28 setembro a 2 outubro 1999. Anais. IEEE Computer Society, 1999. pg. 216-219. ISBN 0-7695-0387-X

41. LIMA, Fernanda G.; JOHANN, Marcelo; GÜNTZEL, José Luis.; CARRO, Luigi; REIS, Ricardo Augusto da Luz. A Tool for Analysis of Universal Logic Gates Functionality, In: Symposium on Integrated Circuits and Systems Design, 12, Natal, RN, 28 setembro a 2 outubro 1999. Anais. IEEE Computer Society, 1999. pg. 184-187. ISBN 0-7695-0387-X

42. PRADO, Alex; STTEMMER, Gaspar; AGOSTINI, Luciano; CAMPOS, Tatiane; PACHECO, Roberto; REIS, Ricardo; BAMPI, Sérgio. Projeto de um Circuito Integrado Cancelador de Eco-Siseco In: SEXTO WORKSHOP IBERCHIP, São Paulo, March 15-17, 2000. p. 316.

43. JOHANN, Marcelo; CARRO, Luigi; REIS, Ricardo, Automatic Master-Slice Generation with Garota In: SEXTO WORKSHOP IBERCHIP, São Paulo, March 15-17, 2000. p. 355-360

44. MARTINS, João B., MONTEIRO, José; REIS, Ricardo. ESTIMAÇÃO DE CAPACITANCIAS E POTÊNCIA DE CIRCUITOS CMOS A NÍVEL LÓGICO In: SEXTO WORKSHOP IBERCHIP, São Paulo, March 15-17, 2000. p. 70-79

45. LIMA, Fernanda G.; LUBASZEWSKI, Marcelo; REIS, Ricardo A. L. A Self-Testing Mask Programmable Matrix Using Built-In Current Sensing. In: LATW 2000 IEEE Latin-American Test Workshop. Rio de Janeiro, March 12-14, 2000. Pg.15-19

46. MAYER, U.; HOLLSTEIN T.; BECKER J.; GLESNER M.; INDRUSIAK, L.; REIS, R. An Internet-Capable CAD Suite for the Mulit-Level Design of Complex Microelectronic Systems, In: DATE 2000 - Design Automation and Test in Europe Conference, User Forum, Paris, March 27-30, 2000

47. MACHADO, Júlio P.; MORAIS, Carlos T. Q.; MENEZES, Paulo B.; REIS, Ricardo. Structuring Web Course Pages as Automata: Revising Concepts, RIAO2000 - Computer-Assisted Information Retrieval, Paris, France, April, 12-14, 2000, CASIS, 2000. Vol.1, p.150-159. ISBN 2-905450-07-X.

48. BECKER J.; MAYER, U.; GLESNER M.; INDRUSIAK, L.; REIS, R. Providing Flexible Internet for FPGA-Based CAD Courses, In: EWME 2000 - 3rd European Workshop on Microelectronics Education, Aix-en-Provence, France, May 18-19, 2000.

49. LIMA, Fernanda G.; BARCELOS, M; ROCHOL, J.; BAMPI, S.; REIS, Ricardo A. L. A Frame Stream Controller IP. In: ISCAS 2000 IEEE International Symposium on Circuits and Systems. Genebra, Suiça, May 28-31, 2000.

50. MARTINS, João B., MONTEIRO, José; REIS, Ricardo Accurate Modeling of Capacitance and Power in Logic Level Circuits, ACM International Workshop on Logic Synthesis 2000 (IWLS00), Dana Point, June 2000.

51. FERREIRA, Fábio Klein; MORAES, Fernando.; REIS, Ricardo Fast Interconnect Parasitic Extraction in Deep Submicron Using Bin-Based Algorithm, 43th IEEE Midwest Symposium on Circuits and Systems, IEEE Circuits and Systems Society, Michigan, USA, 9-12 Agosto 2000, p.1148-1151. ISBN: 0-7803-6475-9.

52. MORAIS, Carlos T. Q.; MACHADO, Júlio P.; MENEZES, Paulo B.; REIS, Ricardo. A Web Teaching System Based on Formal Methods, ICEUT2000 - International Conference on Educational Uses of Communication and Information Technologies, IFIP World Computer Congress, Beijing, China, August, 21-25, 2000

53. MARTINS, João B., MONTEIRO, José; REIS, Ricardo. Capacitance and Power Modeling at Logic-Level, ICDA2000 - International Conference on Chip Design Automation, IFIP World Computer Congress, Beijing, China, August, 21-25, 2000

54. MORAIS, Carlos T. Q.; MACHADO, Júlio P.; MENEZES, Paulo B.; REIS, Ricardo. Modelagem para Geração Automática de Exercícios e Avaliações, ICECE2000 - International Conference on Engineering and Computer Education, São Paulo, August 27-30, 2000

55. FRAGOSO, João; MORAES, Fernando REIS, Ricardo. WTROPIC: a Macro-cell Generator on World Wide Web In: Symposium on Integrated Circuits and Systems Design, 13, Manaus, AM, 18 a 24 de setembro 2000. Anais. IEEE Computer Society, 2000. Pg. 133-138 ISBN: 0-7695-0843-X

56. FERREIRA, Fábio; MORAES, Fernando; REIS, Ricardo. LASCA - Interconnect Parasitic Extraction Tool for Deep-Submicron IC Design In: Symposium on Integrated Circuits and Systems Design, 13, Manaus, AM, 18 a 24 de setembro 2000. Anais. IEEE Computer Society, 2000. Pg. 327- 332. ISBN: 0-7695-0843-X

57. INDRUSIAK, Leandro; REIS, Ricardo. From a Hyperdocument-Centric to an Object-Oriented Approach for the Cave Project. In: Symposium on Integrated Circuits and Systems Design, 13, Manaus, AM, 18 a 24 de setembro 2000. Anais. IEEE Computer Society, 2000. Pg. 125-130. ISBN: 0-7695-0843-X

58. LIMA, Fernanda, COTA E.; CARRO, Luigi; LUBASZEWSKI, Marcelo; REIS, Ricardo; VELAZCO, Raoul; REZGUI, Sana. Designing a Radiation Hardened 8051-like Micro-controller. In: Symposium on Integrated Circuits and Systems Design, 13, Manaus, AM, 18 a 24 de setembro 2000. Anais. IEEE Computer Society, 2000. Pg. 255-260 ISBN: 0-7695-0843-X

59 - STEMMER, Gaspar; AGOSTINI, Luciano; PRADO, Alex; PACHECO, Roberto; CAMPOS, Tatiane; BAMPI, Sérgio; REIS, Ricardo; SisECO: Design of an Echo-Canceling IC for Base Band Modens. In: Symposium on Integrated Circuits and Systems Design, 13, Manaus, AM, 18 a 24 de setembro 2000. Anais. IEEE Computer Society, 2000. pg 216-221. ISBN: 0-7695-0843-X

60 - GÜNTZEL, José; PINTO, Ana C.; d'ÁVILA E.; REIS, Ricardo ATG-Based Timing Analysis of Circuits Containing Complex Gates In: Symposium on Integrated Circuits and Systems Design, 13, Manaus, AM, 18 a 24 de setembro 2000. Anais. IEEE Computer Society, 2000. Pg. 21-26 ISBN: 0-7695-0843-X

61 - JOHANN, Marcelo; REIS, Ricardo. Net by Net Routing with a New Path Search Algorithm. In: Symposium on Integrated Circuits and Systems Design, 13, Manaus, AM, 18 a 24 de setembro 2000. Anais. IEEE Computer Society, 2000.pg. 144-149 ISBN: 0-7695-0843-X

62. LIMA, Fernanda, COTA E.; CARRO, Luigi; LUBASZEWSKI, Marcelo; REIS, Ricardo; VELAZCO, Raoul; REZGUI, Sana. Designing and Testing a Radiation Hardened 8051-like Micro-controller. MAPLD2000 - The 3rd annual Military and Aerospace Applications of Programmable Devices and Technologies International Conference, Maryland, USA, September 26-28, 2000.

63. INDRUSIAK, L.S.; REIS, R.A.L.; BECKER, J.; GLESNER, M. DInCAD: Distributed Internet-based CAD Methods for Future Complex Microelectronic Systems, VI German-Brazilian Workshop on Information Technology. BMBF / CNPq, Recife, Brasil, September 27 –29, 2000. Proceedings pg. 188-194.

64. JOHANN, Marcelo; CADWELL, A.; KAHNG, Andrew; REIS, Ricardo A New Bidirectional Heuristic Shortest Path Search Algorithm In: International ICSC Congress on Intelligent Systems and Aplications, Wollongong, Austrália, December 11-15, 2000. CD Ref: 1514-185, ISBN 3-906454-24-X

65. GÜNTZEL, José L.; PINTO, Ana; REIS, Ricardo. A Timed Calculus for ATG-Based Timing Analysis with Complex Gates. In: LATW2001- IEEE Latin-American Test Workshop, Cancun. February 11-14, 2001, Proceedings, pg. 234-239

66. AGOSTINI, L. V.; STEMMER, G. H.; BAMPI, S.; REIS, R. A Dedicated 20 x 3 bit Multiplier Using the Recoding Principle for Echo Cancellation. In: DATE 2001 - Design, Automation & Test in Europe - Designer´s Forum, March 13-16, 2001, Munich - Germany. pg. 73-76.

67. HERNANDEZ, Emmerson, SAWICKI, Sandro; INDRUSIAK, Leandro; REIS, Ricardo. Homero-Um Editor VHDL Cooperativo Via Web In: VII WORKSHOP IBERCHIP, Montevideo - Uruguai, March 21-23, 2001.

68 - OST, Luciano; MAINARDI, Marcos; INDRUSIAK, Leandro; REIS, Ricardo. Jale3D - Platform-independent IC/MEMS Layout Edition Tool. In: Symposium on Integrated Circuits and Systems Design, 14, Pirenópolis, GO, 10 a 14 de setembro 2001. Anais. IEEE Computer Society, 2001.pg. 174-179, ISBN 0-7695-1333-6

69 - MARTINS, João B.; MORAES, Fernando; REIS, Ricardo. Interconnection Length Estimation at Logic-Level. In: Symposium on Integrated Circuits and Systems Design, 14, Pirenópolis, GO, 10 a 14 de setembro 2001. Anais. IEEE Computer Society, 2001.pg. 98-102. ISBN 0-7695-1333-6

70 - JOHANN, Marcelo; REIS, Ricardo. LEGAL: An Algorithm for Simultaneous Net Routing. In: Symposium on Integrated Circuits and Systems Design, 14, Pirenópolis, GO, 10 a 14 de setembro 2001. Anais. IEEE Computer Society, 2001.pg. 180-185. ISBN 0-7695-1333-6

71. LIMA, Fernanda; REZGUI, Sana; CARRO, Luigi; VELAZCO, Raoul; REIS, Ricardo. On the Use of VHDL Simulation and Emulation to Derive Error Rate. In: RADECS 2001 - RADiation and its Effects on Components and Systems. September 10-14, 2001, Grenoble, France.

72. LIMA, Fernanda; Carmichael, C., Fabula, J.; Padovani, R.; REIS, Ricardo. A Fault Injection Analysis of Virtex FPGA TMR Design Methodology. In: RADECS 2001 - RADiation and its Effects on Components and Systems. September 10-14, 2001, Grenoble, France.

73. INDRUSIAK, L.S.; BECKER, J.; GLESNER, M. REIS, R.A.L.; Distributed Collaborative Design over Cave2 Framework, VLSI-SOC2001 IFIP WG10.5 Conference on Very Large Scale Systems, December 3-5, 2001. Montpellier, France, Proceedings.

74. GUNTZEL, J. L., WILKE, G., BYSTRONSKI, M., PINTO, A. C. M., REIS, R. A. L. A Comparison Between Testability Measures Applied to Complex Gates. In: 3º Latin- American Test Workshop - LATW, 2002, Montevideu. Proceedings LATW2002. , 2002. v.1. p.144 - 149

75. INDRUSIAK, L., GLESNER, M., REIS, R. A. L. Collaborative Learning by Sharing Design Experience In: 4th European Workshop on Microelectronics Education - EWME, 2002, Vigo. Proceedings. , 2002

76. INDRUSIAK, L. S., GLESNER, M., REIS, R. A. L. Comparative Analysis and Application of Data Repository Infraestructure for Collabaration-enable Distributed Design Enviroments In: DATE2002- Design, Automation and Test in Europe: Designer´s Forum, 2002, Paris. Proceedings DATE 2002. Los Alamitos: IEEE Computer Society, 2002. v.1. p.1130 - 1130

77. BARCELOS, M., PANATO, A., REIS, R. A. L. Design case: optimized performance and area implementation of advanced encryption standard in Altera devices In: Proceedings DesignCon 2002, Santa Clara.

78. LIMA, F., CARRO, L., VELAZCO, R., REIS, R. A. L. Inject Multiple Upsets in A SEU Tolerant 8051 Micro-controller In: IEEE On-Line Testing Workshop, 2002, Bendor. On-Line Testing Workshop. Los Alamitos: IEEE Computer Society Press, 2002. v.1. p.194 – 194.

79. LIMA, F., CARRO, L., VELAZCO, R., REIS, R. A. L. Injecting Multiple Upsets in a SEU Tolerant 8051 Micro Controler In: 3º Latin- American Test Workshop - LATW, 2002, Montevideo. Proceedings LATW 2002, 2002. v.1. p.120 - 125

80. BRISOLARA, L., INDRUSIAK, L. S., REIS, R. A. L. Modelagem Orientada de Primitivas de Projeto de Sistemas Eletronicos para Colaboração In: Oitavo Workshop Iberchip, 2002, Guadalajara. Proceedings Oitavo Workshop Iberchip, 2002.

81. SAWICKI, S., INDRUSIAK, L., REIS, R. A. L. Projeto Cooperativo no Ambiente CAVE In: Oitavo Workshop Iberchip, 2002, Guadalajara. Proceedings Oitavo Workshop Iberchip. , 2002.

82. BARCELOS, M., PANATO, A., REIS, R. A. L. Um IP de Criptografia Padrão Rijdael para Projeto em FPGA In: Oitavo Workshop Iberchip, 2002. Guadalajara. Proceedings Oitavo Workshop Iberchip. , April 2002.

83. GIRARDI, A., MENEZES, C., LAZZARI, C., CORTES, F. P., BRITO, J., HENTSCHKE, R., UBIRATANAN, R., REIS, R. A. L. Um hardware IP para Criptografia no Padrão AES-Rijandael In: Oitavo Workshop Iberchip, 2002, Guadalajara, Proceedings Oitavo Workshop Iberchip. , April 2002.

84 - JOHANN, M., SANTOS, G., REIS, R. A. L. A Legal Algorithm Following Global Routing In: Chip in the Pampa, 2002, PORTO ALEGRE. 15th Symposium on Integrated Circuits and Systems Design. Los Alamitos: IEEE Computer Society Press, 2002. v.1. p.271 – 276.

85 - PANATO, A., BARCELOS, M., REIS, R. A. L. An IP an Advanced Encryption Standard for Altera Devices In: Chip in the Pampa, 2002, Porto Alegre. 15th Symposium on Integrated Circuits and Systems Design. Los Alamtos: IEEE Computer Society Press, 2002. v.1. p.197 -202.

86 - HENTSCHKE, R., MARQUES, R., LIMA, F., CARRO, L., SUZIM, A., REIS, R. A. L. Analizyng Area and Performance Penalty of Protecting Different Digital Modules with Hamming code and Triple Modular Redundancy. In: Chip in the Pampa, Porto Alegre. 15th Symposium on Integrated Circuits and Systems Design. Los Alamitos: IEEE Society Computer Press, 2002. v.1. p.95 - 100

87 - SAWICKI, S., BRISOLARA, L., INDRUSIAK, L., REIS, R. A. L. Collaborative Design Using a Shared Object Spaces Infrastructures In: Chip in the Pampa, 2002, Porto Alegre. 15th Symposium on Integrated Circuits and System Design. Los Alamitos: IEEE Computer Society Press, 2002. v.1. p.163 – 168.

88 - WILKE, G., GUNTZEL, J. L., BYSTRONSKI, M., PINTO, A. C., REIS, R. A. L. Finding the Critical Delay of Combination Block by Floating Vector Simulation and Path Tracing In: Chip in the Pampa, 2002, Porto Alegre. 15th Symposium on Integrated Circuits and Systems Design. Los Alamitos: IEEE Computer Society Press, 2002. v.1. p.277 – 288.

89. GUNTZEL, J. L., WILKE, G.; PINTO, A. C. M.; REIS, R. A. L. A Delay Enumeration-Based Timing Analysis Algorithm In: 4º Latin- American Test Workshop - LATW 2003, Natal, Proceedings LATW 2003.

90. LIMA, F., CARRO, L., REIS, R. A. L. Single Event Upset Mitigation Techniques for SRAM Based FPGAs In: 4º Latin- American Test Workshop - LATW 2003, Natal, Proceedings LATW 2003.

91. LAZZARI, C.; PANATO, A.; NEUBERGER, G.; LIMA, F.; REIS, R. A. L. Designing a Fault Tolerant AES Rijndael Soft IP Core In: 4º Latin- American Test Workshop - LATW 2003, Natal, Proceedings LATW 2003.

92. NEUBERGER, G.; LIMA, F., CARRO, L., REIS, R. A. L. A Multiple Bit Upset Tolerant SRAM Memory In: 4º Latin- American Test Workshop - LATW 2003, Natal, Proceedings LATW 2003.

93. LIMA, F., CARRO, L., REIS, R. A. L. Reducing Pin and Area Overhead in Fault-Tolerant FPGA-based Designs In: IEEE Eleventh International Symposium on Field Programmable Gate Arrays, February 2003, Monterey, USA.

94. PANATO, A., BARCELOS, M., REIS, R. A. L. A Low Device Occupation IP to Implement Rijndael Algorithm In: DATE2003- Design, Automation and Test in Europe: Designers Forum, 2003, Munich. Proceedings DATE 2003 Designer’s Forum. Los Alamitos: IEEE Computer Society, 2003.

95. INDRUSIAK, L. S., LUBITZ, F., REIS, R. A. L., GLESNER, M., Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues In: DATE2003- Design, Automation and Test in Europe, March 2003, Munich. Proceedings DATE 2003. Los Alamitos: IEEE Computer Society, 2003.

96. HENTSCHKE, R.; FIORENTIN, D., MORAES, F., REIS, R. A. L Comparação de Posicionamento Simulated Annealing e Quadratura no Gerador Automático de Macro-Células Tropic. In: 9th Workshop Iberchip, 2003, Havana, Proceedings 9th Workshop Iberchip, March 2003.

97. HENTSCHKE, R.; FIORENTIN, D., REIS, R. A. L Uma Comparação do Processo de Low Annealing Com High Annealing Aplicado ao Posicionamento de Células. In: 9th Workshop Iberchip, 2003, Havana, Proceedings 9th Workshop Iberchip. , March 2003.

98. INDRUSIAK, L. S., GLESNER M., REIS, R. A. L., Computational Infrastructure for the Collaborative Design of Integrated Systems in a Distributed Environment, CCE03 - CHALLENGES IN COLLABORATIVE ENGINEERING, 15 th -16 th April 2003, Poznan, Poland p.101-108, Publishing House of Poznan University of Technology, ISBN 8371434952

99. HENTSCHKE, R.; REIS, R. A. L., Pic-Plac: A Novel Constructive Algorithm for Placement, IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, May 25-28, 2003.

100. CASACURTA, A., ALMEIDA, M., REIS, R. A Visual Simulation Tool at Layout Level, IEEE Microelectronics System Education, Anaheim, June 1-2, 2003. pp 110-111. ISBN 0-7695-1973-3

101. INDRUSIAK, L. S., REIS, R. A. L., GLESNER, M., ALCÁNTARA G., HÖRMANN S., STEINMETZ R., Reducing Authoring Costs of Online Training In Microelectronics Design by Reusing Design Documentation Content. IEEE Microelectronics System Education, Anaheim, June 1-2, 2003. pp 57-58. ISBN 0-7695-1973-3

102. LIMA, F., CARRO, L., REIS, R. Designing Fault Tolerant Systems into SRAM-based FPGAs. 40th IEEE/ACM DAC, Anaheim, June-2-6, 2003.

103 - HENTSCHKE, R., REIS, R. A. L. Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations. In: Chip in Sampa, São Paulo. 16th Symposium on Integrated Circuits and Systems Design. Los Alamitos: IEEE Society Computer Press, 2003.

104 - SANTOS, C., WILKE, G., LAZZARI, C., REIS, R. A. L. GUNTZEL, J. L. A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. In: Chip in Sampa, São Paulo. 16th Symposium on Integrated Circuits and Systems Design. Los Alamitos: IEEE Society Computer Press, 2003.

105 - FERRÃO, D., WILKE, G., REIS, R. A. L., GUNTZEL, J. L. Improving Critical Path Identification in Functional Timing Analysis. In: Chip in Sampa, São Paulo. 16th Symposium on Integrated Circuits and Systems Design. September 8-13, 2003. Los Alamitos: IEEE Society Computer Press, 2003.

106. REIS, R. Power and Timing Driven Physical Design Automation. PATMOS2003 – 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, Torino, September 10-12, 2003. LNCS Springer Verlag (KEYNOTE SPEAKER)

107. INDRUSIAK, L.S., GLESNER, M., REIS, R. Supporting Consistency Control Between Functional and Structural Views in Interface-based Design Models. In: Forum on Specification and Design Languages (FDL), 23-26 September 2003, Frankfurt.

108. JOHANN, M; HENTSCHKE, R.; REIS, R. A. L A Study on the Performance of Fast Initial Placement Algorithms. IFIP VLSI-SoC2003, Darmstadt, Germany, December 3-5, 2003

109. LAZZARI, C., GUNTZEL, J. L., REIS, R. A. L A New Macro-Cell Generation Strategy for Three Metal Layer CMOS Technologies. IFIP VLSI-SoC2003, Darmstadt, Germany, December 3-5, 2003

110. PANATO, A., SILVA, S.; WAGNER, F.; JOHANN, M; REIS, R., BAMPI, S., Design of Very Deep Pipelined Multipliers for FPGAs , Designer’s Forum, DATE2004, Paris, February 16-20,2004.

111. HENTSCHKE, R.; BECK, A., MATTOS, J., CARRO, L., LUBASZEWSKI, M., REIS, R. Using Genetic Algorithms to Accelerate Automatic Software Generation for Microprocessor Functional Testing. In: 5th Latin- American Test Workshop - LATW 2004, Cartagena, Colombia, March 8-10, 2004

112. NEUBERGER, G.; KASTENSMIDT, F., REIS, R. Improving the Use of Reed-Solomon Codes to Increase Fault-tolerance in Very Deep Sub-Micron Integrated Circuits. In: 5th Latin- American Test Workshop - LATW 2004, Cartagena, Colombia, March 8-10, 2004.

113. FERRAO, D.; SANTOS, G., WILKE, G., GUNTZEL, J., REIS, R. Path Delay Test Generation Using Exact Floating Mode Sensitization. In: 5th Latin- American Test Workshop - LATW 2004, Cartagena, Colombia, March 8-10, 2004

114. SANTOS, G., SANTOS, C., HENTSCHKE, R., GIRARDI, A., REIS, R. Uma Ferramenta para Geração Automática de Módulos de Memórias ROM, In: 10th Workshop Iberchip, 2004, Cartagena, Colombia, Proceedings, March 10-12, 2004.

115. HENTSCHKE, R.; REIS, R. Blue Macaw: A Didactic Placement Tool Using Simulated Annealing, In: 10th Workshop Iberchip, 2004, Cartagena, Colombia, Proceedings, March 10-12, 2004.

116. SILVA, S.; PANATO, A., WAGNER, F.; REIS, R., BAMPI, S., Implementação em FPGA de um Multiplicador de Ponto Flutuante com Pipeline Profundo, In: 10th Workshop Iberchip, 2004, Cartagena, Colombia, Proceedings, March 10-12, 2004.

117. REIS, R., KASTENSMIDT, F., GUNTZEL, J.; Physical Design Methodologies for Performance Predictability and Manufacturability. IN: ACM 2004 International Conference Computing Frontiers, Ischia, Italia, April 14-16, 2004

118. KASTENSMIDT, F., NEUBERGER, G.; CARRO, L., REIS, R. A. L. Designing and Testing Fault-Tolerant Techniques for SRAM-based FPGAs. IN: ACM 2004 International Conference on Computing Frontiers, Ischia, Italia, April 14-16, 2004

119. INDRUSIAK, L.S., GLESNER, M., KREUTZ, M., SUSIN, A., REIS, R., UML-Driven Design Space Delimitation and Exploratation: A Case Study on Networks-on-Chip, IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS2004, April 18-21, 2004, Tatranská Lomnica, Eslovaquia p. 5-12. ISBN 8096911791

120 - MURGAN, T., SCHLACHTA, C., PETROV, M., INDRUSIAK, L., GARCIA, A., GLESNER, M., REIS, R. A. L. Accurate Capture of Timing Parameters in On-Chip Interconnects In: Chip on the Reefs, 2004, Porto de Galinhas. 17th Symposium on Integrated Circuits and System Design. ACM Press, 2004. p.117 – 122. ISBN 1-58113-947-0

121. BASTIAN F., LAZZARI, C., GUNTZEL, J. L., REIS, R. A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool, PATMOS2004, 14th International Workshop on Power and Timing Modeling, Optimization and Simulation, Santorini, September 15-17, 2004. LNCS 3254 Springer. p. 732-741. ISSN 0302-9743 ISBN 3-540-23095-5

122. BRISOLARA, L.; BECKER, L.; CARRO, L.; WAGNER, F.; PEREIRA, C.; REIS, R.; Comparing High-level Modeling Approaches for Embedded System Design, ASP-DAC 2005, Asian South-Pacific Design Automation Conference (IEEE/ACM), January 18-21, 2005, Shangai, China.

123. NEUBERGER, G.; KASTENSMIDT, F., WIRTH, G., REIS, R. Analyzing Transient Fault Effects in the Periphery Logic of SRAM Memories. In: 6th Latin- American Test Workshop - LATW 2005, Salvador de Bahia, Brazil, March 30-April 2, 2005. p. 46-50.

124. NEVES, C.; FERRÀO, D.; BRAGA, M.; AGOSTINI, L.; REIS, R. GUNTZEL, J. Hierarchical Timing Analysis Using Selective Critical Path Sensitization. In: 6th Latin- American Test Workshop - LATW 2005, Salvador de Bahia, Brazil, March 30-April 2, 2005. p. 65-70.

125. LAZZARI, C.; ANGHEL, L., REIS, R. Soft Error Circuit Hardening Techniques Implementation Using an Automatic Layout Generator. In: 6th Latin-American Test Workshop - LATW 2005, Salvador de Bahia, Brazil, March 30-April 2, 2005. p. 175-180.

126. BECK, A.; HENTSCHKE, R.; MATTOS, L., REIS, R.; CARRO, L. Fast and Efficient Test Generation for Embedded Stack Processors. In: 6th Latin- American Test Workshop - LATW 2005, Salvador de Bahia, Brazil, March 30-April 2, 2005. P.331-336.

127. INDRUSIAK, L.S., GLESNER, REIS, R , Embedding Version-Based Asynchronous Collaboration Support in A Design Data Model Implemented As Object-Oriented Framework 3rd Workshop on Challenges in Collaborative Engineering CCE05, Sopron, Hungary, April 14-15, 2005

128. SANTOS, C.; FERRÃO, D.; GUNTZEL, J. REIS, R. A. L., Incremental Timing Optimization for Automatic Layout Generation, IEEE International Symposium on Circuits and Systems, ISCAS2005, Kobe, Japan, May 23-26, 2005. p. 3567-3570. ISBN: 0-7803-8834-8

129. LAZZARI, C.; ANGHEL, L., REIS, R. On Implementing a Soft Error Hardening Technique By Using an Automatic Layout Generator: Case Study. In: 11th IEEE International On-Line Testing Symposium - IOLTS 2005, Saint Raphael, France, July 6-8, 2005. Pg. 29-34, IEEE CS Press, ISBN 0-7695-2406-0

130. INDRUSIAK, L.S., MURGAN, T., GLESNER, M., REIS, R , Consistency Control in Data-driven Design Automation Environments, IEEE 6th International Symposium on Signals Circuits and Systems - ISSCS 2005, Iasi, Romenia, July 14-15, 2005.

131. SANTOS, C.; FERRÀO, D.; WILKE, G.; LAZZARI, C.; GUNTZEL, J. REIS, R. Effects of Using a Pin-to-Pin Delay Model on a Library-Free Transistor/Gate Sizing Scheme, 48th IEEE International Midwest Symposium on Circuits & Systems, Cincinnati, Ohio, Aug 7 - 10, 2005, p. 315-318, ISBN: 0-7803-9197-7, DOI 10.1109/MWSCAS.2005.159410

132 - PALMA, J,; MARCON, C.; REIS, R. A. L.; SUSIN, A.; MORAES, F., CALAZANS, N.. Mapping Embedded Systems onto NoCs - The Traffic Effect on Dynamic Energy Estimation In: Chip on the Island, 2005, Florianópolis. 18th Symposium on Integrated Circuits and System Design. ACM Press, 2005. p.196-201, ISBN 1-59593-174-0

133. BASTOS, R.; KASTENSMIDT, F.; REIS, R. Designing Low Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory; PATMOS 2005; Leuven, Belgium; 20-23 September, 2005. LNCS 3728, pg. 59-68, Springer, ISSN 0302-9743

134. LAZZARI, C., ANGHEL. L., REIS, R. A. L A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming. IFIP VLSI-SoC2005, Perth, Australia, October 17-19, 2005

135. MARCON, C.; PALMA, J,; CALAZANS, N.; MORAES, F., SUSIN, A.; REIS, R. A. L Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. IFIP VLSI-SoC2005, Perth, Australia, October 17-19, 2005

136. OLIVEIRA, L., SANTOS. C.; FERRÃO, D.; COSTA, E.; MONTEIRO, J.; MARTINS, J.; BAMPI, S.; REIS, R. A. L A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. IFIP VLSI-SoC2005, Perth, Australia, October 17-19, 2005

137. HENTSCHKE, R.; JOHANN, M.; REIS, R. BLUE MACAW: A Didactic Placement Tool using Simulated Annealing, In: IFIP EDUTECH 2005. Perth, Australia, October 20-21, 2005

138. ROLT, J., WIRTH, G., KASTENSMIDT, F.; REIS, R. Analyzing the Effect of CMOS Process Variability on the SRAM Cell Sensitivity to SEU. In: 7th Latin- American Test Workshop - LATW 2006, Buenos Aires, Argentina, March 27- 29, 2006.

139. BASTOS, R., WIRTH, G., KASTENSMIDT, F.; REIS, R. Design of a Robust 8-Bit Microprocessor to Soft Single Event Effects. In: 7th Latin- American Test Workshop - LATW 2006, Buenos Aires, Argentina, March 27- 29, 2006.

140. MENEZES, C., MEINHARDT, C., REIS, R. A. L., TAVARES, R., A Regular Layout Approach for ASICs. In: ISVLSI2006. IEEE Computer Society Annual Symposium on VLSI, Karlsruhe, Germany, March 2-3, IEEE CS Press, 2006.

141. PALMA, J., INDRUSIAK, L.S., MORAES, F., ORTIZ, A., GLESNER, M., REIS, R. A. L., Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip. In: ISVLSI2006. IEEE Computer Society Annual Symposium on VLSI, Karlsruhe, Germany, March 2-3, IEEE CS Press, 2006.

142. INDRUSIAK, L. S.; GLESNER, M.; REIS, R. A. L., A Taxonomy for the Collaborative Design of Integrated Electronic Systems, In: Challenges in Collaborative Engineering Workshop, 2006, Prague. Proceedings, Jönköping: Jönköping University, 19-20 April, 2006. p. 85-93. ISBN 91-975604-3X

143. FERRÃO, D., WILKE, G., REIS, R. A. L., NEVES, C., AGOSTINI, L., GUNTZEL, J. L. Safe Path-Based Hierarchical Functional Timing Analysis by Considering Block Arrival Times. In: ICCDCS2006. IEEE 6th International Caribbean Conference on Devices, Circuits and Systems, Play del Carmen, Mexico, April 26-28, 2006, IEEE Press, ISBN 1-4244-0042-2, pg. 345-349, DOI: 10.1109/ICCDCS.2006.250885.

144. MENEZES, C., MEINHARDT, C., REIS, R. A. L., TAVARES, R., Design of Regular Layouts to Improve Predictability. In: ICCDCS2006. IEEE 6th International Caribbean Conference on Devices, Circuits and Systems, Play del Carmen, Mexico, April 26-28, 2006. IEEE Press, ISBN 1-4244-0042-2 , pg. 67-72. DOI: 10.1109/ICCDCS.2006.250839

145. SANTOS, G., JOHANN, M., REIS, R.A. L., Channel Based Routing in Channel-less Circuits. IEEE International Symposium on Circuits and Systems. ISCAS2006, Kos, Greece, May 21-24, 2006. IEEE Press. 4 pp., ISBN: 0-7803-9389-9, DOI: 10.1109/ISCAS.2006.1692591.

146. LAZZARI, C., REIS, R., ANGHEL, L., Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study, IEEE On-Line Test Symposium – IOLTS2006, Como, Itália, July 2006, IEEE Press, 6 pp., ISBN: 0-7695-2620-9, DOI 10.1109/IOLTS.2006.48.

147. BASTOS, R., KASTENSMIDT, F., REIS, R. Design of a Robust 8-Bit Microprocessor to Soft Single Event Effects. IEEE On-Line Test Symposium – IOLTS2006, Como, Itália, July 2006, IEEE Press. 2 pp., ISBN: 0-7695-2620-9, DOI: 10.1109/IOLTS.2006.21.

148. SAWICKI, S.; HENTSCHKE, R.; JOHANN, M.; REIS, R, An Algorithm for I/O Pins Partitioning Targeting 3D VLSI Integrated Circuits, 49th IEEE International Midwest Symposium on Circuits and Systems, San Juan, Porto Rico, August 7-9, 2006. IEEE Press.

149. SAWICKI, S.; HENTSCHKE, R.; JOHANN, M.; REIS, R., Um Algoritmo para o Particionamento de Pinos de I/O em Circuitos VLSI 3D, Conferencia Latino Americano de Informática – CLEI2006, Santiago, Chile, August 21 - 25, 2006

150 - HENTSCHKE, R., FLACH, G.; PINTO, F.; REIS, R. A. L., Quadratic Placement for 3D Circuits Using Z-Cell Shifting, 3D Iterative Refinement and Simulated Annealing. In: Chip on the Mountains, 2006, Ouro Preto. 19th Symposium on Integrated Circuits and System Design. ACM Press, 2006.

151 - BASTOS, R., KASTENSMIDT, F.; REIS, R. Design at High Level of a Robust 8-Bit Microprocessor to Soft Errors by Using Only Standard Gates. In: Chip on the Mountains, 2006, Ouro Preto. 19th Symposium on Integrated Circuits and System Design. ACM Press, 2006.

152. PALMA, J., INDRUSIAK, L.S., MORAES, F., ORTIZ, A., GLESNER, M., REIS, R. A. L, Adaptive Coding in Networks-on-Chip: Transition Activity Reduction versus Power Overhead of the Codec Circuitry, PATMOS’06 - 16th International Workshop on Power and Timing Modeling, Optimization and Simulation, Montpellier, France, September 13-15, 2006, LNCC, Springer.

153. FERRÃO, D., REIS, R. A. L., GUNTZEL, J., Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis, PATMOS’06 - 16th International Workshop on Power and Timing Modeling, Optimization and Simulation, Montpellier, France, September 13-15, 2006, LNCC, Springer.

154. NEUBERGER, G., KASTENSMIDT, F., REIS, R., WIRTH, G., BREDERLOW, R., PACHA, C. Statistical Characterization of Hold Time Violations in 130nm CMOS Technology, 32nd European Solid-State Circuits Conference - ESSCIRC2006, September 18-22, 2006, Montreux, Switzerland. P. 114-117, ISSN: 1930-8833, ISBN: 1-4244-0303-0, DOI: 10.1109/ESSCIR.2006.307544.

155. HENTSCHKE, R.; SAWICKI, S.; JOHANN, M.; REIS, R., An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias. IFIP VLSI-SoC2006, Nice, França, October 16-18, 2006. P. 128-133. ISBN: 3-901882-19-7, DOI 10.1109/VLSISOC.2006.313216.

156. LAZZARI, C., SANTOS, C., REIS, R., A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits, 13th IEEE International Conference on Electronics, Circuits and Systems – ICECS2006, Nice, France, December 10 - 13, 2006, p. 660-663, ISBN: 1-4244-0395-2, DOI 10.1109/ICECS.2006.379875.

157. TAVARES, R.. MEINHARDT, C., REIS, R., OrBDDs Direct Mapping for Structured Logic Circuits, 13th IEEE International Conference on Electronics, Circuits and Systems – ICECS2006, Nice, France, December 10 - 13, 2006, p. 1057 – 1060, ISBN: 1-4244-0395-2, DOI 10.1109/ICECS.2006.379620.

158. SAWICKI, S.; HENTSCHKE, R.; JOHANN, M.; REIS, R., Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits, 13th IEEE International Conference on Electronics, Circuits and Systems – ICECS2006, Nice, France, December 10 - 13, 2006, p. 399 – 402, ISBN: 1-4244-0395-2, DOI 10.1109/ICECS.2006.379809.

159. HORNA, C. T., RAMOS, F., BARCELOS, M., REIS, R. Implementação e Validação de IP Soft Cores para Interfaces Ethernet 10/100 E 1000 Mbps Sobre Dispositivos Reconfiguráveis, In: 13th Workshop Iberchip, 2007, Lima, Peru Proceedings, pg. 276-281, March 14-16, 2007. ISBN: 978-9972-242-09-0

160. PALMA, J., INDRUSIAK, L.S., MORAES, F., ORTIZ, A., GLESNER, M., REIS, R. Avaliando o Impacto de Técnicas De Codificação de Dados Sobre o Consumo de Potência em Networks-On-Chip, In: 13th Workshop Iberchip, 2007, Lima, Peru, Proceedings, pg. 413- 418, March 14-16, 2007. ISBN: 978-9972-242-09-0

161. ANMARI, R., LEVEUGLE, R., ANGHEL, L., LAZZARI, C.; REIS, R. SET Fault Injection Methods in Analog Circuits: Case Study. In: 8th Latin- American Test Workshop - LATW 2007, Cuzco, Peru, March 12-14, 2007.

162. NEUBERGER, G., KASTENSMIDT, F., REIS, R., WIRTH, G., BREDERLOW, R., PACHA, C.. Statistical Analysis of Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies. In: 8th Latin- American Test Workshop - LATW 2007, Cuzco, Peru, March 12-14, 2007.

163. HENTSCHKE, R., NARASIMHAM, J., JOHANN, M., REIS, R. Maze Routing Steiner Trees with Effective Critical Sink Optimization. In: ISPD2007. ACM/IEEE International Symposium on Physical Design, Texas, USA, March 18-21, 2007. Pg. 135-142, ISBN 978-1-59593-613-4, DOI 10.1145/1231996.1232024.

164. BRISOLARA, L., GUERIN, X., CARRO, L., REIS, R., CHAC, S., JERRAYA, A. Reducing Fine-grain Communication Overhead in Multithread Code Generation for Heterogeneous MPSoC. In: SCOMP2007, Nice, France, April 9-11, 2007.

165. BRUSAMARELLO, L., SILVA, R., WIRTH, G., REIS, R. Yield Analysis by Error Propagation Using Higher Order Derivatives Considering WD and D2D Variations. In: ISVLSI2007. IEEE Computer Society Annual Symposium on VLSI, Porto Alegre, Brazil, May 9-11, IEEE CS Press, 2007. P. 86 – 91, ISBN: 0-7695-2896-1, DOI: 10.1109/ISVLSI.2007.102.

166. HENTSCHKE, R., FLACH, G., PINTO, F., REIS, R. 3D-Vias Aware Quadratic Placement for 3D VLSI Circuits. In: ISVLSI2007. IEEE Computer Society Annual Symposium on VLSI, Porto Alegre, Brazil, May 9-11, IEEE CS Press, 2007. P. 67-72, ISBN: 0-7695-2896-1, DOI: 10.1109/ISVLSI.2007.1.

167. PALMA, J., INDRUSIAK, L.S., MORAES, F., ORTIZ, A., GLESNER, M., REIS, R.. Inserting Data Encoding Techniques into NoC-Based Systems. In: ISVLSI2007. IEEE Computer Society Annual Symposium on VLSI, Porto Alegre, Brazil, May 9-11, IEEE CS Press, 2007. P. 299 – 304, ISBN: 0-7695-2896-1, DOI: 10.1109/ISVLSI.2007.58.

168. HENTSCHKE, R., JOHANN, M., REIS, R.A. L., Channel Based Routing in Channel-less Circuits. IEEE International Symposium on Circuits and Systems. ISCAS2007, New Orleans, USA, May 27-30, 2007. IEEE Press. pp. 2036 – 2039, ISBN: 1-4244-0921-7, DOI 10.1109/ISCAS.2007.378497

169. TAVARES, R., REIS, R. A Simple Approach to Partition a Set of Logic Input Variables, IWLS2007, San Diego, May 30 – June 1, 2007.

170. TAVARES, R., LAUTENSCHLÄGER, W., REIS, R., A CAL Tool to Aid the Understanding of Logic Synthesis, MSE2007, Microelectronics Systems Education, June 3-4, 2007, San Diego, USA, p. 49-50, ISBN: 0-7695-2849-X, DOI 10.1109/MSE.2007.5

171. ZIESEMER, A.; LAZZARI, C., REIS, R., An Educational Tool for Design Automation of CMOS Cells, MSE2007, Microelectronics Systems Education, June 3-4, 2007, San Diego, USA. p. 149-150, ISBN: 0-7695-2849-X , DOI 10.1109/MSE.2007.19

172. FLACH, G., JOHANN, M.; HENTSCHKE, R.; REIS, R. Cell Placement on Graphics Processing Unit, In: Chip in Rio, 2007, Rio de Janeiro. 20th Symposium on Integrated Circuits and System Design. ACM Press, 2007. P. 87-92, ISBN:978-1-59593-816-9, DOI 10.1145/1284480.1284510.

173. BRUSAMARELLO, L., SILVA, R., WIRTH, G., REIS, R. Obtainint Delay Distribution of Dynamic Logic Circuits by Error Propagation at The Electrical Level, In: IFIP/CEDA VLSI-SoC2007, International Conference on Very Large Scale Integration, Atlanta, USA, October 15-17, 2007. pp. 94-98, ISBN: 978-1-4244-1710-0 , DOI 10.1109/VLSISOC.2007.4402479.

174. NEUBERGER, G., KASTENSMIDT, F., REIS, R., WIRTH, G., BREDERLOW, R., PACHA, C., Statistical Analysis of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90 nm CMOS Technologies, In: IFIP/CEDA VLSI-SoC2007, International Conference on Very Large Scale Integration, Atlanta, USA, October 15-17, 2007. pp. 78-83, ISBN: 978-1-4244-1710-0, DOI 10.1109/VLSISOC.2007.4402476.

175. ZIESEMER, A.; LAZZARI, C., REIS, R., Transistor Level Automatic Layout Generator for non-Complementary CMOS Cells, In: IFIP/CEDA VLSI-SoC2007, International Conference on Very Large Scale Integration, Atlanta, USA, October 15-17, 2007. pp. 116-121, ISBN: 978-1-4244-1710-0, DOI 10.1109/VLSISOC.2007.4402483

176. LAZZARI, C.; SANTOS, C.; ZIESEMER, A.; ANGHEL, L.; REIS, R., Efficient Timing Closure with a Transistor Level Design Flow, In: IFIP/CEDA VLSI-SoC2007, International Conference on Very Large Scale Integration, Atlanta, USA, October 15-17, 2007. pp. 312-315, ISBN: 978-1-4244-1710-0, DOI 0.1109/VLSISOC.2007.4402520.

177. MEINHARDT, C., REIS, R., TAVARES, R., Logic and Physical Synthesis of Cell Arrays, 14th IEEE International Conference on Electronics, Circuits and Systems – ICECS2007, Marrakesh, Marrocos, December 11 - 14, 2007, p. 1292-1295, ISBN 1424413788

178. PALMA, J., INDRUSIAK, L.S., MORAES, F., REIS, R., GLESNER, M., Reducing the Power Consumption in Networks-on-Chip through Data Coding Schemes, 14th IEEE International Conference on Electronics, Circuits and Systems – ICECS2007, Marrakesh, Marrocos, December 11 - 14, 2007, p. 1007- 1010, ISBN 1424413788.

179. MEINHARDT, C., VIOLANTE, M., REIS, R., REORDA, M., An Experimental Analysis of the Lockstep Architecture on the LEON Case Study, DECIDE 2007, First International Workshop on Dependable Circuit Design, December 6-7, 2007, Buenos Aires, Argentina. P.69-74.

180. LAZZARI, C., ASSIS, T., KASTENSMIDT, F., WIRTH, G., ANGHEL, L., REIS, R., Efficient Transistor Sizing for Soft Error Protection in Combinational Logic Circuits, DECIDE 2007, First International Workshop on Dependable Circuit Design, December 6-7, 2007, Buenos Aires, Argentina, p. 13-18.

181. NEUBERGER, G., REIS, R., WIRTH, G., Protecting Against Flip-Flop Hold Time Violations Due to Process Variations. In: 9th Latin- American Test Workshop - LATW 2008, Puebla, Mexico, February 17- 20, 2008. p. 113-118.

182. FLACH, G., JOHANN, M., REIS, R. Executando Posicionamento Analítico em GPUs, In: 14th Workshop Iberchip, 2008, Puebla, Mexico, Proceedings, February 20-23, 2008. ISBN 9789687938035.

183. PINTO, F., FLACH, G., HENTSCHKE, R., REIS, R. Algoritmo para Evitar vias 3D em Caminhos Críticos, In: 14th Workshop Iberchip, 2008, Puebla, Mexico, Proceedings, February 20-23, 2008. ISBN 9789687938035.

184. SAWICKI, S., HENTSCHKE, R., JOHANN, M., REIS, R. Uma Proposta para o Assinalamento de Pads de I/O e Redução de Vias em Circuitos 3D Baseada em Informações da Estrutura do Circuito, In: 14th Workshop Iberchip, 2008, Puebla, Mexico, Proceedings, February 20-23, 2008. ISBN 9789687938035.

185. LAZZARI, C., ASSIS, T., KASTENSMIDT, F., WIRTH, G., ANGHEL, L., REIS, R., SET-Factor: An Analysis and Design Tool to Reduce SET Sensitivity in Integrated Circuits, ETS 2008, 13th IEEE European Test Symposium, Verbania, Italy, May 25-28, 2008.

186. WILKE, G., FONSECA, R., MEZZOMO, C., REIS, R., A Novel Scheme to Reduce Short-circuit Power in Mesh-based Clock Architectures, In: Chip in the Pampa, 2008, Gramado. 1-4 September 2008, 21st Symposium on Integrated Circuits and System Design. P. 117-122 ACM Press, 2008. ISBN 9781605582320.

187. LAZZARI, C., ASSIS, T., KASTENSMIDT, F., WIRTH, G., REIS, R., ANGHEL, L., An Analysis and Design Technique to Reduce SET Sensitivity in Combinational Integrated Circuits, In: IFIP/IEEE VLSI-SoC2008, International Conference on Very Large Scale Integration, Rhodes, Greece, October 13-15, 2008.ISBN 978-3-901882-32-6

188. REIS, R., Physical Design Automation at Transistor Level, IEEE NORCHIP 2008, Tallin, November 17-18, 2008 (INVITED TALK), p. 241-245, DOI: 10.1109/NORCHP.2008.4738270, ISBN 978-1-4244-2492-4.

189. MEINHARDT, C., VIOLANTE, M., REIS, R., REORDA, M., Recovery Scheme for Hardening System on Programmable Chips, DECIDE 2008, Second International Workshop on Dependable Circuit Design, November 27-29, 2008, Playa Del Carmen, Mexico.

190. ASSIS, T., KASTENSMIDT, F., WIRTH, G., REIS, R., Analysis of Single Event Effects for Different Angles and Impact Regions at a NMOS 90 nm 3D Device, DECIDE 2008, Second International Workshop on Dependable Circuit Design, November 27-29, 2008, Playa Del Carmen, Mexico.

191. MEINHARDT, C., VIOLANTE, M., REIS, R., REORDA, M., Recovery Scheme for Hardening System on Programmable Chips, 10th Latin- American Test Workshop, LATW2009, 2-5 March 2009, Búzios, Rio de Janeiro, Brazil. 6 p., ISBN: 978-1-4244-4206-5

192. ASSIS, T., KASTENSMIDT, F., WIRTH, G., REIS, R., Measuring the Effectiveness of Symmetric and Asymmetric Transistor Sizing for Single Event Transient Mitigation in CMOS 90nm Technologies, 10th Latin- American Test Workshop, LATW2009, 2-5 March 2009, Búzios, Rio de Janeiro, Brazil .6p., ISBN: 978-1-4244-4206-5

193. GHISSONI, S., REIS, R., Otimização de Consumo de Potência e Atraso para Circuitos CMOS Utilizando SCCGs com Topologia Anti-Radiação., In: 15th Workshop Iberchip, 2009, Buenos Aires, Argentina, Proceedings, March 24-27, 2009. p. 77-79. Ediciones Cientificas Americanas, ISBN: 978-987-9486-10-8

194. SAWICKI, S., JOHANN, M., REIS, R., Um Algoritmo de Particionamento Iterativo de Células e Pinos de I/O para Circuito VLSI 3D, In: 15th Workshop Iberchip, 2009, Buenos Aires, Argentina, Proceedings, March 24-27, 2009. p. 103-106. Ediciones Cientificas Americanas, ISBN: 978-987-9486-10-8

195. PINTO, F., CAVALHEIRO, L., REIS, R., Técnica de Posicionamento Dirigido à Redução de Caminhos Críticos, In: 15th Workshop Iberchip, 2009, Buenos Aires, Argentina, Proceedings, March 24-27, 2009. p. 111-115. Ediciones Cientificas Americanas, ISBN: 978-987-9486-10-8

196. LIMA, C., FLACH, G., REIS, R., PlaceDL: Uma Nova Técnica de Espalhamento de Células para Posicionamento Quadrático, In: 15th Workshop Iberchip, 2009, Buenos Aires, Argentina, Proceedings, March 24-27, 2009. p. 116-121. Ediciones Cientificas Americanas, ISBN: 978-987-9486-10-8

197. WILKE, G., FLACH, G., REIS, R., Um método de Otimização para o deslocamento de buffers em redes de relógio do tipo malha, In: 15th Workshop Iberchip, 2009, Buenos Aires, Argentina, Proceedings, March 24-27, 2009. p. 122-126. Ediciones Cientificas Americanas, ISBN: 978-987-9486-10-8

198. MEINHARDT, C., TAVARES, R., REIS, R., Leiautes Regulares Baseados em Matrizes de Células, In: 15th Workshop Iberchip, 2009, Buenos Aires, Argentina, Proceedings, March 24-27, 2009. p. 127-132. Ediciones Cientificas Americanas, ISBN: 978-987-9486-10-8

199. REIMANN, T., SANTOS, G., REIS, R., An Analysis of Predictive Parameters for RC Interconnect Networks, In: 15th Workshop Iberchip, 2009, Buenos Aires, Argentina, Proceedings, March 24-27, 2009. p. 133-137. Ediciones Cientificas Americanas, ISBN: 978-987-9486-10-8

200. GUIMARÃES, D., FRANK, H., GÜNTZEL, J., BAMPI, S., REIS, R., Utilizando um Fluxo ASIC para Integração de um Multiplicador Wallace Tree no Datapath de um Processador RISC, In: 15th Workshop Iberchip, 2009, Buenos Aires, Argentina, Proceedings, March 24-27, 2009. p. 334-337. Ediciones Cientificas Americanas, ISBN: 978-987-9486-10-8

201. ASSIS, T., KASTENSMIDT, F., WIRTH, G., REIS, R., Avaliando a Eficiência do Redimensionamento Simétrico e Assimétrico de Transistores para a Redução de Single Event Effects em uma Tecnologia 90nm CMOS, In: 15th Workshop Iberchip, 2009, Buenos Aires, Argentina, Proceedings, March 24-27, 2009. p. 453-458. Ediciones Cientificas Americanas, ISBN: 978-987-9486-10-8

202. REORDA, M., VIOLANTE, M., MEINHARDT, C., REIS, R., A Low-Cost SEE Mitigation Solution For Soft-Processors Embedded in Systems on Programmable Chips, DATE 2009, Nice, France, April 24-27, 2009.p.352-357, ISBN 978-3-9810-8015-5

203. BASTOS, R., MONNEY, Y., SICARD, G., KASTENSMIDT, F., RENAUDIN M., REIS, R., A Methodology to Evaluate Transient-Fault Effects on Asynchronous and Synchronous Circuits, ETS 2008, 14th IEEE European Test Symposium, Sevilha, Espanha, May 25-28, 2009.

204. BASTOS, R., MONNEY, Y., SICARD, G., KASTENSMIDT, F., RENAUDIN M., REIS, R., Comparing Transient-Fault Effects on Synchronous and on Asynchronous Circuits, IEEE International On-Line Test Symposium, IOLTS 2009, Sesimbra, Portugal, June 24-27, 2009. p. 9-14. ISBN 978-1-4244-4822-7.

205. VAZQUEZ, J., CHAMPAC, V., ZIESEMER A., REIS, R., TEIXEIRA, C., SANTOS, M., TEIXEIRA, J., Built-In Aging Monitoring for Safety-Critical Applications, IEEE International On-Line Test Symposium, IOLTS 2009, Sesimbra, Portugal, June 24-27, 2009. p. 29-34, ISBN 978-1-4244-4822-7.

206. NEUBERGER, G., WIRTH, G., REIS, R., Protecting Digital Circuits Against Hold Time Violation Due to Process Variability, In: Chip on The Dunes, 2009, Natal. 31 August - 3 September 2009, 22nd Symposium on Integrated Circuits and System Design, ACM Press, 2009. ISBN: 978-1-6055-8705-9

207. COTA, E., CARRO, L., PINTO, F., LUBA, M., REIS, R., Resource-and-time-aware Test Strategy for Configurable Quaternary Logic Blocks, In: Chip on The Dunes, 2009, Natal. 31 August - 3 September 2009, 22nd Symposium on Integrated Circuits and System Design, ACM Press, 2009. ISBN: 978-1-6055-8705-9

208. GHISSONI, S., MARTINS, J., REIS, R., MONTEIRO, J., Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates, PATMOS 2009, 19th International Workshop on Power And Timing Modeling, Optimization and Simulation, September 9-11, 2009, Delft, The Netherlands. Springer. LNCC Vol. 5953, 2010, p. 297-306, ISBN 978-3-642-11801-2.

209. ASSIS, T., BRUSAMARELLO, L., KASTENSMIDT, F., WIRTH, G., REIS, R., Transistor Sizing and Folding Techniques for Radiation Hardening, RADECS 2009, September 14-18, Brugge, Belgium, 2009. P. 512-519, ISBN: 978-1-4577-0492-5, DOI: 10.1109/RADECS.2009.5994705

210. REORDA, M., VIOLANTE, M., MEINHARDT, C., REIS, R., An On-Board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Of-The-Shelf SRAM-Based FPGAs, DFT 2009, 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Chicago, USA, October 7-9, 2009.

211. SANTOS, G., REIMANN, T., JOHANN, M., REIS, R., On the Accuracy of Elmore-Based Delay Models. 16th IEEE International Conference on Electronics, Circuits and Systems – ICECS2009, Hammamet, Tunisia, December 13 - 16, 2009. pp. 447- 450. ISBN: 978-1-4244-5091-6.

212. SAWICKI, S., JOHANN, M., REIS, R., A Cells and I/O Pins Partitioning Refinement Algorithm for 3D VLSI Circuits. 16th IEEE International Conference on Electronics, Circuits and Systems – ICECS2009, Hammamet, Tunisia, December 13 - 16, 2009. pp. 852-855. ISBN: 978-1-4244-5091-6.

213. LAZZARI, C., ZIESEMER, A., REIS, R., An Automated Design Methodology for Layout Generation Targeting Power Leakage Minimization. 16th IEEE International Conference on Electronics, Circuits and Systems – ICECS2009, Hammamet, Tunisia, December 13 - 16, 2009. pp. 81-84. ISBN: 978-1-4244-5091-6. ISSN 2177-1286.

214. FRANCK, H.; WILKE, G.; REIS, R.; GÜNTZEL, J.. Somadores Tolerantes a Falhas Usando BSD e Codificação 1 de 3. In: WORKSHOP IBERCHIP, 16 (IBERCHIP 2010). Foz do Iguaçu, Brasil, 23-25 de Fevereiro de 2010. ISSN 2177-1286.

215. BARTRA, W., OSORIO, M., CÁRDENAS, C., REIS, R. Síntesis Física del Módulo de División de N bits con Segmentación v1.10. In: WORKSHOP IBERCHIP, 16 (IBERCHIP 2010). Foz do Iguaçu, Brasil, 23-25 de Fevereiro de 2010. ISSN 2177-1286.

216. SAWICKI, S., JOHANN, M., REIS, R., Migração de Circuitos VLSI 2D para 3D Dirigida a Redução de Interconexões Verticais (TSV), In: WORKSHOP IBERCHIP, 16 (IBERCHIP 2010). Foz do Iguaçu, Brasil, 23-25 de Fevereiro de 2010. ISSN 2177-1286.

217. GUIMARÃES JR, D., CORREA, U., CARRO, L., REIS, R., Estimador de Potência e Atraso em Standard-Cells Utilizando Redes Neurais Artificiais, In: WORKSHOP IBERCHIP, 16 (IBERCHIP 2010). Foz do Iguaçu, Brasil, 23-25 de Fevereiro de 2010. ISSN 2177-1286.

218. MOREIRA, T., GUIMARÃES JR. D., WEHRMEISTER, M., PEREIRA, C. REIS, R., Acelerador em Hardware para Resolução do Despacho de Métodos Polimórficos em Programas Java, In: WORKSHOP IBERCHIP, 16 (IBERCHIP 2010). Foz do Iguaçu, Brasil, 23-25 de Fevereiro de 2010. ISSN 2177-1286.

219. REIMANN, T., SANTOS, G., REIS, R., On Methods for Extraction of Typical Linear Driver Resistance, In: WORKSHOP IBERCHIP, 16 (IBERCHIP 2010). Foz do Iguaçu, Brasil, 23-25 de Fevereiro de 2010. ISSN 2177-1286.

220. MEINHARDT, C., GUEX, J., REIS, R., Estudo do Impacto da Variabilidade em um Conjunto de Blocos Básicos Para Composição de Leiautes Regulares. In: WORKSHOP IBERCHIP, 16 (IBERCHIP 2010). Foz do Iguaçu, Brasil, 23-25 de Fevereiro de 2010. ISSN 2177-1286.

221. VAZQUEZ, J., CHAMPAC, V., ZIESEMER A., REIS, R., TEIXEIRA, I., SANTOS, M., TEIXEIRA, J., Delay Sensing for Parametric Variations and Defects Monitoring in Safety-Critical Applications. In: First IEEE Latin American Symposium on Circuits and Systems – LASCAS 2010, Iguaçu Falls, February 24-26, 2010.

222. POSSER, G., CORRÊA, G., REIS, R., CARRO, L., BAMPI, S., A MIPS-based ASIP to Accelerate the Inverse Hadamard Tranform for H.264/AVC Video Coding. In: First IEEE Latin American Symposium on Circuits and Systems – LASCAS 2010, Iguaçu Falls, February 24-26, 2010.

223. FLACH, G., WILKE, G., JOHANN, M., REIS, R., A Study on Clock Mesh Size Selection, In: First IEEE Latin American Symposium on Circuits and Systems – LASCAS 2010, Iguaçu Falls, February 24-26, 2010.

224. VAZQUEZ, J., CHAMPAC, V., ZIESEMER A., REIS, R., TEIXEIRA, I., SANTOS, M., TEIXEIRA, J., Low-sensitivity to Process Variations Aging Sensor for Automotive Safety-Critical Applications, IEEE VLSI Test Symposium, VTS 2010, Santa Cruz, USA, p. 238-243. April 18-21, 2010. ISSN: 1093-0167. ISBN: 978-1-4244-6649-8, DOI: 10.1109/VTS.2010.5469568.

225. REIS, R., BAMPI, S., Microelectronics Education in the South of Brazil and Outcomes, EWME 2010, 8th European Workshop on Microelectronics Education, Darmstadt, Germany, May 10-12, 2010 (KEYNOTE TALK)

226. GUTHAUS, M., WILKE, G., REIS, R., Non-Uniform Clock Mesh Optimization with Linear Programming Buffer Insertion, IEEE/ACM Design Automation Conference – DAC 2010, p. 74-79, Anaheim, USA, June 12-15, 2010. ISSN: 0738-100X, ISBN: 978-1-4244-6677-1

227. FLACH, G., WILKE, G., JOHANN, M., REIS, R., An Overhead-Free Mesh-Buffer Displacement Optimization Strategy, ISVLSI2010. IEEE Computer Society Annual Symposium on VLSI, Kefalonia, Greece, July 5-7, 2010. P. 282-287, CS Press. ISBN 978-0-7695-4076-4. DOI 10.1109/ISVLSI.2010.108

228. PINTO, F., CAVALHEIRO, L., JOHANN, M., REIS, R., Logical Core Algorithm: Improving Global Placement, ISVLSI2010. IEEE Computer Society Annual Symposium on VLSI, Kefalonia, Greece, July 5-7, 2010. P. 69-73, CS Press. ISBN 978-0-7695-4076-4. DOI 10.1109/ISVLSI.2010.114

229. BASTOS, R., SICARD, G., KASTENSMIDT, F., RENAUDIN M., REIS, R., Evaluating Transient-Fault Effects on Traditional Implementations of the C-element, IEEE International On-Line Test Symposium, IOLTS 2010, Corfu, Greece, July 4-7, 2010. P. 35-40, ISBN: 978-1-4244-7722-7. DOI: 10.1109/IOLTS.2010.5560237

230. VAZQUEZ, J., CHAMPAC, V., ZIESEMER A., REIS, R., SEMIAO, J., TEIXEIRA, I., SANTOS, M., TEIXEIRA, J., Predictive Error Detection by On-line Aging Monitoring, IEEE International On-Line Test Symposium, IOLTS 2010, Corfu, Greece, July 4-7, 2010. P. 9-14, ISBN: 978-1-4244-7722-7 DOI: 10.1109/IOLTS.2010.5560241.

231. SANTOS, G., REIMANN, T., REIS, R., The Fidelity Property of the Elmore Delay Model in Actual Comparison of Routing Algorithms, 28th IEEE International Conference on Computer Design, ICCD 2010, October 3-6, 2010, Amsterdam, Netherlands.

232. REIMANN, T., SANTOS, G., REIS, R., Routing Algorithms Performance in Different Routing Scopes. 17th IEEE International Conference on Electronics, Circuits and Systems – ICECS2010, Athens, Greece December 13 - 16, 2010. p. 649-652, ISBN: 978-1-4244-8156-9, DOI: 10.1109/ICECS.2010.5724594

233. TONFAT, J., REIS, R., Design and Verification of a Layer-2 Ethernet Mac Classification Engine for a Gigabit Ethernet Switch. 17th IEEE International Conference on Electronics, Circuits and Systems – ICECS2010, Athens, Greece, December 12 - 15, 2010. p. 146-149, ISBN: 978-1-4244-8156-9

234. POSSER, G., ZIESEMER, A., GUIMARÃES JR, D., WILKE, G., REIS, R., A Study on Layout Quality of Automatic Generated Cells. 17th IEEE International Conference on Electronics, Circuits and Systems – ICECS2010, Athens, Greece, December 12 - 15, 2010. p. 657-660, ISBN: 978-1-4244-8156-9

235. GHISSONI, S., REIS, R., Radix-2 Decimation in Time (Dit) FFT Implementation Based on Matrix-Multiple Constant Multiplication Approach. 17th IEEE International Conference on Electronics, Circuits and Systems – ICECS2010, Athens, Greece, December 12 - 15, 2010. p. 861-864, ISBN: 978-1-4244-8156-9

236. POSSER, G., FLACH, G., WILKE, G., REIS, R., Gate Sizing using Geometric Programming. In: Second IEEE Latin American Symposium on Circuits and Systems – LASCAS 2011, Bogotá, February 23-25, 2011, 4 p., ISBN 978-1-4244-9484-2. DOI 10.1109/LASCAS.2011.5750263

237. TONFAT, J., REIS, R., Diseño y Verificación de un Motor de Clasificación de Capa 2 MAC Ethernet para un Conmutador Gigabit Ethernet, In: WORKSHOP IBERCHIP, 17 (IBERCHIP 2011). Bogotá, Colombia, 23-25 de Fevereiro de 2011. 4p., ISSN 2177-1286.

238. REIMANN, T., SANTOS, G., REIS, R., Desempenho de Algoritmos de Roteamento em Diferentes Cenários de Interconexão, In: WORKSHOP IBERCHIP, 17 (IBERCHIP 2011). Bogotá, Colombia, 23-25 de Fevereiro de 2011. 4p., ISSN 2177-1286.

239. POSSER, G., ZIESEMER, A., GUIMARÃES JR, D., WILKE, G., REIS, R., Estudo da Qualidade do Leiaute de Células Geradas Automaticamente, In: WORKSHOP IBERCHIP, 17 (IBERCHIP 2011). Bogotá, Colombia, 23-25 de Fevereiro de 2011. 5 p., ISSN 2177-1286.

240. BARTRA, W., KASTENSMIDT, F., REIS, R., Pacote de Simulação de SETs e SEUs utilizando LabVIEW, In: WORKSHOP IBERCHIP, 17 (IBERCHIP 2011). Bogotá, Colombia, 23-25 de Fevereiro de 2011. 6 p., ISSN 2177-1286.

241. TONFAT, J., NEUBERGER, G., REIS, R., Functional Verification of Logic Modules for a Gigabit Ethernet Switch, 12th Latin- American Test Workshop, LATW2011, 27-30 March 2011, Porto de Galinhas, Pernambuco, Brazil. ISBN: 978-1-4577-1489-4, DOI 10.1109/LATW.2011.5985930, 10.1109/LATW.2011.5985930

242. REIS, R., Design Automation of Transistor Networks, a New Challenge. IEEE International Symposium on Circuits and Systems, ISCAS2011, Rio de Janeiro, Brasil, May 15-19, 2011. IEEE Press. p. 2485-2488, ISBN: 978-1-4244-9472-9. DOI 10.1109/ISCAS.2011.5938108

243. POSSER, G., FLACH, G., WILKE, G., REIS, R., Gate Sizing Minimizing Delay and Area, ISVLSI2011. IEEE Computer Society Annual Symposium on VLSI, Chennai, India, July 4-6, 2011. p. 315-316, ISBN 978-0-7695-4447-2. DOI 10.1109/ISVLSI.2011.92

244. REIS, R., Power Consumption & Reliability in NanoCMOS, IEEE NANO, 11th International Conference on Nanotechnology, Portland, USA, August 15-19, 2011 (invited talk). p.711-714. ISBN 978-1-4577-1515-0, DOI: 10.1109/NANO.2011.6144656

245. FLACH, G., JOHANN, M., REIS, R., One-Iteration Linear System Solver for Quadratic Placement, SBCCI2011, 24th Symposium on Integrated Circuits and System Design, ACM Press, João Pessoa, August 30-September 2, 2011. P. 109-112, ISBN: 978-1-4503-0828-1, DOI: 10.1145/2020876.2020902

246. BARTRA, W., REIS, R., SET and SEU Simulation Toolkit for LabVIEW, RADECS 2011, Conference on RADIATION EFFECTS on COMPONENTS and SYSTEMS, Seville, Spain, September 19-23, 2011, p. 829-836, ISBN: 9781457705878, DOI 10.1109/RADECS.2011.6131342

247. CHIPANA, R., KASTENSMIDT, F., TONFAT, J., REIS, R., GUTHAUS, M., SET Susceptibility Analysis in Buffered Tree Clock Distribution Networks, RADECS 2011, Conference on RADIATION EFFECTS on COMPONENTS and SYSTEMS, Seville, Spain, September 19-23, 2011, p. 256-261, ISBN: 9781457705878, DOI: 10.1109/RADECS.2011.6131404

248. GHISSONI, S., COSTA, E, MONTEIRO, J., REIS, R., Combination of Constant Matrix Multiplication and Gate-Level Approaches for Area and Power Efficient Hybrid Radix-2 DIT FFT Realization. 18th IEEE International Conference on Electronics, Circuits and Systems – ICECS2011, Beirut, Libano, December 12 - 15, 2011. p. 567-570. ISBN: 9781457718465, 10.1109/ICECS.2011.6122338

249. SCARTEZINNI, G., REIS, R., Power Consumption in Transistor Networks Versus in Standard Cells. 18th IEEE International Conference on Electronics, Circuits and Systems – ICECS2011, Beirut, Lebanon, December 11 - 14, 2011. p. 740-743. ISBN: 978-1-4577-1846-5, DOI 10.1109/ICECS.2011.6122380

250. POSSER, G., FLACH, G., WILKE, G., REIS, R., Dimensionamento de Portas Lógicas e de Transistores Minimizando Atraso e Área, In: WORKSHOP IBERCHIP, 18 (IBERCHIP 2012). Playa del Carmem, Mexico, 29 de Fevereiro a 2 de Março de 2012. 4p., ISSN 2177-1286.

251. FERLA, T., FLACH, G., REIS, R., Uma Ferramenta Educacional para o Ensino de Simulated Annealing e Posicionamento. In: WORKSHOP IBERCHIP, 18 (IBERCHIP 2012). Playa del Carmem, Mexico, 29 de Fevereiro a 2 de Março de 2012. 4p., ISSN 2177-1286.

252. BARTRA, W., KASTENSMIDT, F., REIS, R., Simulación de Fallas SET en un Oscilador Controlado por Voltaje. In: WORKSHOP IBERCHIP, 18 (IBERCHIP 2012). Playa del Carmem, Mexico, 29 de Fevereiro a 2 de Março de 2012. 4p., ISSN 2177-1286.

253. SCARTEZINNI, G., REIS, R., Dissipação de Potência em Redes de Transistores versus Células Padrão. In: WORKSHOP IBERCHIP, 18 (IBERCHIP 2012). Playa del Carmem, Mexico, 29 de Fevereiro a 2 de Março de 2012. 4p., ISSN 2177-1286.

254. POSSER, G., FLACH, G., WILKE, G., REIS, R., Tradeoff Between Delay and Area in the Gate Sizing using Geometric Programming. In: Third IEEE Latin American Symposium on Circuits and Systems – LASCAS 2012, Playa del Carmen, February 29- March 2, 2012, 4 p. ISBN: 9781467312080, 10.1109/LASCAS.2012.6180332

255. MEINHARDT, C., REIS, R., Evaluation of Process Variability on Current for Nanotechnologies Devices. In: Third IEEE Latin American Symposium on Circuits and Systems – LASCAS 2012, Playa del Carmen, February 29- March 2, 2012, 4 p. ISBN: 978-1-4673-1208-0, DOI: 10.1109/LASCAS.2012.6180361

256. TONFAT, J., REIS, R., Low Power 3-2 and 4-2 Adder Compressors Implemented Using ASTRAN. In: Third IEEE Latin American Symposium on Circuits and Systems – LASCAS 2012, Playa del Carmen, February 29- March 2, 2012, 4 p. ISBN: 978-1-4673-1208-0, 10.1109/LASCAS.2012.6180303

257. FLACH, G., CONCEIÇÃO, C., JOHANN, M., REIS, R., Revisiting Atari 2600 on an FPGA, VIII Southern Conference on Programmable Logic, SPL 2012, Bento Gonçalves, Brazil, March 21-23, 2012. ISBN: 9781467301848, DOI: 10.1109/SPL.2012.6211805

258. CONCEICAO, C., REIS, R., Quantum Algorithms Simulation on FPGAs, SPL 2012 Designer’s Forum, Bento Gonçalves, Brazil, March 21-23, 2012.

259. BARTRA, W. REIS, R., Simulation of SET Faults in a Voltage Controlled Oscillator, 13th IEEE Latin American Test Workshop, LATW 2012, April 10-13, 2012, Quito, Equador. DOI: 10.1109/LATW.2012.6261230

260. CHIPANA, R., KASTENSMIDT, F., TONFAT, J., REIS, R., Set Susceptibility Estimation of Clock Tree Networks from Layout Extraction, 13th IEEE Latin American Test Workshop, LATW 2012, April 10-13, 2012, Quito, Equador. DOI: 10.1109/LATW.2012.6261256

261. TAVARES, R., REIS, R., DLS: A Didactic Logic Synthesis Tool, 9th EWME - European Workshop on Microelectronics Education, May 9-11, 2012, Grenoble, France. pp. 18-21, ISBN: 978-2-35500-019-5.

262. BARTRA, W. REIS, R., An Educational Tool Kit for SET and SEU Fault Simulation, 9th EWME - European Workshop on Microelectronics Education, May 9-11, 2012, Grenoble, France. pp. 113-118, ISBN: 9782355000195.

263. SCARTEZINNI, G., REIS, R., Synthesis of Transistor Networks as an Option to Standard Cells, IWLS – International Symposium on Logic Synthesis, June 1-3, Berkeley, USA. p. 89-92.

264. POSSER, G., FLACH, G., WILKE, G., REIS, R., Transistor Sizing and Gate Sizing Using Geometric Programming Considering Delay Minimization, NEWCAS 2012, 10th IEEE International NEWCAS Conference, June 17-20, 2012, Montreal, Canada. p. 85-88. ISBN: 9781467308588

265. CHIPANA, R., CHIELLE, E., KASTENSMIDT, F., TONFAT, J., REIS, R., Soft-Error Probability Due to SET in Clock Tree Networks, ISVLSI2012. IEEE Computer Society Annual Symposium on VLSI, Amherst, USA, August 19-21, 2012. p.338-343. ISBN: 978-0-7695-4767-1, DOI: 10.1109/ISVLSI.2012.39

266. SANTOS, C., REIS, R., GODOI, G., BARROS, M., DUARTE, F., Multi-Bit Flip-Flop Usage Impact on Physical Synthesis, SBCCI2012, 25th Symposium on Integrated Circuits and System Design, ACM Press, Brasilia, August 30-September 2, 2012. p.57- 62, ISBN 978-1-4673-2608-7.

267. GHISSONI, S., COSTA, E, MONTEIRO, J., REIS, R., Efficient Area and Power Multiplication Part of FFT Based on Twiddle Factor Decomposition. 19th IEEE International Conference on Electronics, Circuits and Systems – ICECS2012, Sevilha, Spain, December 9 - 12, 2012. P.657-660. ISBN: 978-1-4673-1259-2. DOI: 10.1109/ICECS.2012.6463640

268. GUARESCHI, W., AZAMBUJA, J., KASTENSMIDT, F., REIS, R., DURÃO, O., SCHUCH, N., DESSBESEL, G., A Configurable Test Bed Design for Nanosatellites to Qualify Commercial and Customized Integrated Circuits, 34th IEEE Aerospace Conference, Big Sky, Montana, USA, March 2-9, 2013. ISBN: 978-1-4673-1811-2, DOI: 10.1109/AERO.2013.6497170

269. MEINHARDT, C., REIS, R., FinFET Basic Cells Evaluation for Regular Layouts. In: Fourth IEEE Latin American Symposium on Circuits and Systems – LASCAS 2013, Cusco, Peru, February 27- March 1, 2013, 4 p. ISBN: 978-1-4673-4897-3, DOI: 10.1109/LASCAS.2013.6519063

270. BARTRA, W., REIS, R., Estudo e Desenvolvimento dos Algoritmos de Busca de Caminhos em Grafos no LabVIEW. In: WORKSHOP IBERCHIP, 19 (IBERCHIP 2013). Cusco, Peru, 27 de Fevereiro a 1 de Março de 2013. 4p., ISSN 2177-1286.

271. TONFAT, J., FERLA, T., FLACH, G., REIS, R., Improving Run Time of EDA Algorithms With FPGAs: SAT Solver As Case Study. In: WORKSHOP IBERCHIP, 19 (IBERCHIP 2013). Cusco, Peru, 27 de Fevereiro a 1 de Março de 2013. 4p., ISSN 2177-1286.

272. MIRANDA, M., CONCEIÇÃO, C., REIS, R., Demonstrando o Algoritmo de Busca Quântica de Grover. In: WORKSHOP IBERCHIP, 19 (IBERCHIP 2013). Cusco, Peru, 27 de Fevereiro a 1 de Março de 2013. 4p., ISSN 2177-1286.

273. CONCEIÇÃO, C., REIS, R., Geração Automática de Processadores Dedicados à Simulação de Algoritmos Quânticos em FPGA. In: WORKSHOP IBERCHIP, 19 (IBERCHIP 2013). Cusco, Peru, 27 de Fevereiro a 1 de Março de 2013. 4p., ISSN 2177-1286.

274. REIMANN, T., POSSER, G., FLACH, G., JOHANN, G., REIS, R., Dimensionamento de Portas e Assinalamento de Vt usando Fanin/Fanout e Simulated Annealing. In: WORKSHOP IBERCHIP, 19 (IBERCHIP 2013). Cusco, Peru, 27 de Fevereiro a 1 de Março de 2013. 4p., ISSN 2177-1286.

275. GUARESCHI, W., AZAMBUJA, J., KASTENSMIDT, F., REIS, R., DURÃO, O., SCHUCH, N., DESSBESEL, G., Projeto de uma Plataforma para Teste e Qualificação de Circuitos Integrados para Satélites, In: WORKSHOP IBERCHIP, 19 (IBERCHIP 2013). Cusco, Peru, 27 de Fevereiro a 1 de Março de 2013. 4p., ISSN 2177-1286.

276. REIMANN, T., POSSER, G., FLACH, G., JOHANN, G., REIS, R., Simultaneous Gate Sizing and Vt Assignment Using Fanin/Fanout Ratio and Simulated Annealing. IEEE International Symposium on Circuits and Systems, ISCAS2013, Beijing, China, May 19-23, 2013. P. 2549-2552, IEEE Press. ISBN 978-1-4673-5762-3, 10.1109/ISCAS.2013.6572398

277. TARRILO, J., TONFAT, J., REIS, R., KASTENSMIDT, F., BRUGUIER, F., BOURRÉE, M., BENOIT, P., TORRES, L., Using Electromagnetic Emanations for Variability Characterization in Flash-Based FPGAs, ISVLSI2013. IEEE Computer Society Annual Symposium on VLSI, Natal, Brazil, August 5-7, 2013. p. 10.1109/ISVLSI.2013.6654631

278. FLACH, G., REIMANN, T., POSSER, G., JOHANN, G., REIS, R., Simultaneous Gate Sizing and Vth Assignment using Lagrangian Relaxation and Delay Sensitivities, ISVLSI2013. IEEE Computer Society Annual Symposium on VLSI, Natal, Brazil, August 5-7, 2013. p. 10.1109/ISVLSI.2013.6654627

279. NUNES, L., REIS, R., Global Routing Congestion Reduction with Cost Allocation Look-ahead, SBCCI2013, 26th Symposium on Integrated Circuits and System Design, ACM Press, Curitiba, September 2-6, 2013. ISBN: 9781479911325, DOI: 10.1109/SBCCI.2013.6644889

280. TONFAT, J., AZAMBUJA, J., NAZAR, G., RECH, P., FROST, C., KASTENSMIDT, F., CARRO, L., REIS, R., BENFICA, J., VARGAS, F., BEZERRA, E., Analyzing the Influence of Voltage Scaling for Soft Errors in SRAM-based FPGAs, RADECS2013, Conference on RADIATION EFFECTS on COMPONENTS and SYSTEMS, Oxford, England, September 23-27, 2013.

281. NUNES, L., REIMANN, T., REIS, R., GR-PA: A Cost Pre-Allocation Model For Global Routing, In: IFIP/IEEE VLSI-SoC2013, International Conference on Very Large Scale Integration, Istambul, Turkey, October 5-7, 2013. 10.1109/VLSI-SoC.2013.6673264

282. SANTOS, C., VIVET, P., DUTOIT, D., GARRAULT, P., PELTIER, N., REIS, R., System-Level Thermal Modeling for 3D Circuits: Characterization with a 65nm Memory-on-Logic Circuit, 3DIC – 3rd IEEE , October 3-5, 2013, San Francisco, USA, 10.1109/3DIC.2013.6702379

283. TERRES, M., MEINHARDT, C., BONTORIN, G., REIS, R., A Novel Approach to Reduce Power Consumption in Level Shifter for Multiple Dynamic Supply Voltage, 20th IEEE International Conference on Electronics, Circuits and Systems – ICECS2013, Abu Dhabi, UEA, December 8 - 11, 2013. P. 715-718. DOI 10.1109/ICECS.2013.6815514

284. Kologeski, A., Concatto, C., Matos, D., Grehs, D., Motta, T., Almeida, F., Kastensmidt, F., Susin, A., Reis, R., Combining Fault Tolerance and Serialization Effort to Improve Yield in 3D Networks-on-Chip, 20th IEEE International Conference on Electronics, Circuits and Systems – ICECS2013, Abu Dhabi, UEA, December 8 - 11, 2013. P. 125-128. 10.1109/ICECS.2013.6815370

285. ROSA, F., OST, L., REIS, R., Instruction-Driven Timing CPU Model for Efficient Embedded Software Development Using OVP, 20th IEEE International Conference on Electronics, Circuits and Systems – ICECS2013, Abu Dhabi, UEA, December 8 - 11, 2013. p. 855-858. 10.1109/ICECS.2013.6815549

286. BARTRA, W., REIS, R., ANGHEL, C., VLADIMIRESCU, A., Impact of SEU on Bulk and FDSOI CMOS SRAM, EUROSOI2014, 10th Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits, January 27-19, 2014, Terragona, Spain.

287. FLACH, G., REIMANN, T., POSSER, G., JOHANN, M., REIS, R., Dimensionamento de Portas e Assinalamento de Vth Simultâneos usando Relaxação Lagrangiana, In: WORKSHOP IBERCHIP, 20 (IBERCHIP 2014). Santiago de Chile, February 25-28, 2014. 4p., ISSN 2177-1286.

288. CAPUTO, R., JOHANN, M., BONTORIN, G., REIS, R., Design Automation for Digital Microfluidic Biochips, In: WORKSHOP IBERCHIP, 20 (IBERCHIP 2014). Santiago de Chile, February 25-28, 2014. 4p., ISSN 2177-1286.

289. NUNES, L., REIMANN, T., REIS, R., Técnicas de Pré-Alocação de Custo Para Roteamento Global de Circuitos VLSI, In: WORKSHOP IBERCHIP, 20 (IBERCHIP 2014). Santiago de Chile, February 25-28, 2014. 4p., ISSN 2177-1286.

290. POSSER, G., BELOMO, J., SAPATNEKAR, S., REIS, R., Dimensionamento de Transistores para dispositivos MOSFETs e FinFETs, In: WORKSHOP IBERCHIP, 20 (IBERCHIP 2014). Santiago de Chile, February 25-28, 2014. 4p., ISSN 2177-1286.

291. PEREIRA, L., BUTZEN, P., MEINHARDT, C., REIS, R., Análise do Desempenho de Circuitos Somadores Tolerantes a Falhas baseado em Projeto Diversitário, In: WORKSHOP IBERCHIP, 20 (IBERCHIP 2014). Santiago de Chile, February 25-28, 2014. 4p., ISSN 2177-1286.

292. MACHADO, I., BUTZEN, P., MEINHARDT, C., REIS, R., Caracterização Elétrica Automática de Portas Lógicas CMOS Explorando um Algoritmo Guloso, In: WORKSHOP IBERCHIP, 20 (IBERCHIP 2014). Santiago de Chile, February 25-28, 2014. 4p., ISSN 2177-1286.

293. FOGAÇA, M., MEINHARDT, C., BUTZEN, P., REIS, R., Uma comparação entre schedules de temperatura na meta-heurística Simulated Annealing aplicada a posicionamento de células em circuitos VLSI, In: WORKSHOP IBERCHIP, 20 (IBERCHIP 2014). Santiago de Chile, February 25-28, 2014. 4p., ISSN 2177-1286.

294. TERRES, M., MEINHARDT, C., BONTORIN, G., REIS, R., Exploring More Efficient Architectures for Multiple Dynamic Supply Voltage Designs. In: Fith IEEE Latin American Symposium on Circuits and Systems – LASCAS 2014, Santiago de Chile, February 25-28, 2014, 4 p. 10.1109/LASCAS.2014.6820313

295. MEINHARDT, C., REIS, R., Comparing High-Performance Cells in CMOS Bulk and FinFET Technologies. In: Fith IEEE Latin American Symposium on Circuits and Systems – LASCAS 2014, Santiago de Chile, February 25-28, 2014, 4 p. 10.1109/LASCAS.2014.6820310

296. ZIESEMER, A., REIS, R., MOREIRA, M., ARENDT, M., CALAZANS, N., Automatic Layout Synthesis with Astran Applied to Asynchronous Cells. In: Fith IEEE Latin American Symposium on Circuits and Systems – LASCAS 2014, Santiago de Chile, February 25-28, 2014, 4 p. 10.1109/LASCAS.2014.6820314

297. TAMBARA, L., TONFAT, J., REIS, R., KASTENSMIDT, F., PEREIRA JUNIOR, E., VAZ, R., GONCALEZ, O., Soft Error Rate in SRAM-based FPGAs under Neutron-induced and TID Effects, 15th IEEE Latin American Test Workshop, LATW 2014, March 12-15, 2014, Fortaleza, Brazil. 6 p., DOI: 10.1109/LATW.2014.6841920

298. FERLA, T., FLACH, G., REIS, R., A Tool to Simulate Optical Lithography in NanoCMOs, I2MTC 2014 – 31st IEEE International Instrumentation and Measurement Technology Conference, May 12-15, 2014, Montevideo, Uruguay. p. 1471 - 1474, ISBN: 978-1-4673-6385-3, DOI 10.1109/I2MTC.2014.6860989

299. BARTRA, W., REIS, R., A Set of Virtual Instruments to Simulate Radiation Effects in CMOS Circuits, I2MTC 2014 – 31st IEEE International Instrumentation and Measurement Technology Conference, May 12-15, 2014, Montevideo, Uruguay. p. 1643 - 1646, ISBN: 978-1-4673-6385-3, DOI: 10.1109/I2MTC.2014.6861024

300. KASTENSMIDT, F., TONFAT, J., BOTH, T., RECH, P., WIRTH, G., REIS, R., BRUGUIER, F., BENOIT, P., TORRES, L., FROST, C., Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs, ETS2014, 19th IEEE European Test Symposium, May 26-30, 2014, Paderborn, Germany. DOI 10.1109/ETS.2014.6847845

301. ZIESEMER, A., REIS, R., MOREIRA, M., ARENDT, M., CALAZANS, N., A Design Flow for Physical Synthesis of Digital Cells with ASTRAN, GLSVLSI 2014, 24th Great Lakes Symposium on VLSI, May 21-23, 2014, Houston, Texas, USA. P.245-246. ISBN: 978-1-4503-2816-6, DOI: 10.1145/2591513.2591577

302. ZIESEMER, A., REIS, R., Simultaneous Two-Dimensional Cell Layout Compaction Using MILP with ASTRAN, ISVLSI2014 - IEEE Computer Society Annual Symposium on VLSI, July 9-11, 2014, Tampa, USA, p. 350-355, ISBN: 978-1-4799-3765-3, DOI 10.1109/ISVLSI.2014.79

303. POSSER, G., BELOMO, J., MEINHARDT, C., REIS, R., Performance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices, ISVLSI2014 - IEEE Computer Society Annual Symposium on VLSI, July 9-11, 2014, Tampa, USA, p. 418-423, ISBN: 978-1-4799-3765-3, DOI 10.1109/ISVLSI.2014.13

304. BARTRA, W., REIS, R., ANGHEL, C., VLADIMIRESCU, A., Bulk and FDSOI SRAM Resiliency to Radiation Effects, MWSCAS, IEEE 57th International Midwest Symposium on Circuits and Systems, August 3-6, 2014, College Station, Texas, USA, p.655-658. ISBN 978-1-4 799-4133-9 DOI: 10.1109/MWSCAS.2014.6908500

305. MOREIRA, M., ARENDT, M., ZIESEMER, A., REIS, R., CALAZANS, N., Automated Design of Asynchronous Cells, 27th Symposium on Integrated Circuits and System Design, Aracaju, September 1-5, 2014. P.183-188. ISBN 978-1-4503-3156-2.

306. SANTOS, C., VIVET, P., MATTER, G., PELTIER, N., KAISER, S., REIS, R., Thermal Modeling Methodology for Efficient System-Level Thermal Analysis, IEEE CICC – Custom Integrated Circuits Conference, September 14-17, 2014, San Jose, USA

307. TONFAT, J., AZAMBUJA, J., NAZAR, G., RECH, P., KASTENSMIDT, F., CARRO, L., REIS, R., BENFICA, J., VARGAS, F., BEZERRA, E., FROST, C., Analyzing the Influence of Voltage Scaling for Soft Errors in SRAM-based FPGAs, IMS3TW – 19th IEEE Mixed-Signals, Systems, and Sensors Test Workshop, September 17-19, 2014, Porto Alegre, Brazil, ISBN 978-1-4799-6540-3

308. ZIMPECK, A., MEINHARDT, C., REIS, R., Evaluating the Impact of Environment and Physical Variability on the Current of 20nm FinFET, PATMOS 2014, 24th International Workshop on Power And Timing Modeling, Optimization and Simulation, September 29 to October 1, 2014, Palma de Mallorca, Spain. ISBN 978-1-4799-5412-4

309. ROSA, F., OST, L., RAUPP, T., MORAES, F., REIS, R., Fast Energy Evaluation of Embedded Applications for Many-core Systems, PATMOS 2014, 24th International Workshop on Power And Timing Modeling, Optimization and Simulation, September 29 to October 1, 2014, Palma de Mallorca, Spain. ISBN 978-1-4799-5412-4

310. BRUNI, G., RECH, P., TAMBARA, L., NAZAR, G., KASTENSMIDT, F., REIS, R., PACCAGNELLA, A., Power Dissipation Effects on 28nm Fpga-Based SoC Neutron Sensitivity, IFIP/IEEE VLSI-SoC2014, International Conference on Very Large Scale Integration, Playa del Carmen, Mexico, October 6-8, 2014

311. POSSER, G., MISHRA, V., JAIN, P., REIS, R., SAPATNEKAR, S., A Systematic Approach for Analyzing and Optimizing Cell-Internal Signal Electromigration, ICCAD 2014 – 33rd IEEE/ACM International Conference on Computer-Aided Design, November 3-6, San Jose, USA. p. 486-491, ISBN: 978-1-4799-6278-5

312. SANTOS, C., VIVET, P., COLONNA, J.-P., COUDRAIN, P., REIS, R., Thermal Performance of 3D ICs: Analysis and Alternatives, 3DIC – 4th IEEE EEE International Conference on 3D System Integration, December 1-3, 2014, Cork, Ireland.

313. SANTOS, C., SOUARE, P., COUDRAIN, P., COLONNA, J.-P., CRECY, F., VIVET, P., BORBELY, A., REIS, R., JAMAA, H., FIORI, V., FARCY, A., Using TSVs for Thermal Mitigation in 3D Circuits: Wish and Truth, 3DIC – 4th IEEE EEE International Conference on 3D System Integration, December 1-3, 2014, Cork, Ireland.

314. SANTOS, C., VIVET, P., REIS, R., Thermal Impact of 3D Stacking and Die Thickness: Analysis and Characterization of a Memory-on-Logic Circuit, 21th IEEE International Conference on Electronics, Circuits and Systems – ICECS2014, Marseille, France, December 7 - 10, 2014. ISBN: 978-1-4799-4243-5

315. POSSER, G., MISHRA, V., REIS, R., SAPATNEKAR, S., Analyzing the Electromigration Effects on Different Metal Layers and Different Wire Lengths, 21th IEEE International Conference on Electronics, Circuits and Systems – ICECS2014, Marseille, France, December 7 - 10, 2014. ISBN: 978-1-4799-4243-5

316. MEINHARDT, C., ZIMPECK, A., REIS, R., Impact of Gate Workfunction Fluctuation on FinFET Standard Cells, 21th IEEE International Conference on Electronics, Circuits and Systems – ICECS2014, Marseille, France, December 7 - 10, 2014. P. 574-577, ISBN: 978-1-4799-4243-5

317. REIMANN, T., SZE, C., REIS, R., Gate Sizing and Threshold Voltage Assignment for High Performance Microprocessor Designs, 20th Asia and South Pacific Design Automation Conference, ASPDAC 2015, Chiba, Japan, January 19-22, 2015 (invited paper). ISBN: 978-1-4799-7792-5

318. CONCEIÇÃO, C., REIS, R., Efficient Emulation of Quantum Circuits on Classical Hardware, In: Sixth IEEE Latin American Symposium on Circuits and Systems – LASCAS 2015, Montevideo, February 24-27, 2015. ISBN: 978-1-4799-8331-5

319. TUMELERO, D., BONTORIN, G., REIS, R., Overhead for Independent Net Approach for Global Routing, In: Sixth IEEE Latin American Symposium on Circuits and Systems – LASCAS 2015, Montevideo, February 24-27, 2015.

320. BARTRA, W., REIS, R., VLADIMIRESCU, A., Modeling the Impact of Heavy Ion on FDSOI NanoCMOS, In: Sixth IEEE Latin American Symposium on Circuits and Systems – LASCAS 2015, Montevideo, February 24-27, 2015

321. POSSER, G., PARIS, L., MISHRA, V., JAIN, P., REIS, R., SAPATNEKAR, S., Reducing the Signal Electromigration Effects on Different Logic Gates by Cell Layout Optimization, In: Sixth IEEE Latin American Symposium on Circuits and Systems – LASCAS 2015, Montevideo, February 24-27, 2015. DOI: 10.1109/LASCAS.2015.7250429

322. FLACH, G., PUGET, J., MONTEIRO, J., FOGAÇA, M., JOHANN, M., BUTZEN, P., AND REIS, R., Jezz: An Incremental Legalizer, In: XXI IBERCHIP Workshop, Montevideo, February 24-27, 2015. ISSN 2177-1286

323. ZIMPECK, A., MEINHARDT, C., REIS, R., Análise do Impacto da Variabilidade Física nas correntes ION e IOFF de dispositivos FinFET sub 20nm, In: XXI IBERCHIP Workshop, Montevideo, February 24-27, 2015

324. BARTRA, W., REIS, R., Estudo e Implementação do Algoritmo Simulated Annealing para Posicionamento de Células utilizando LabVIEW, In: XXI IBERCHIP Workshop, Montevideo, February 24-27, 2015

325. POSSER, G., PARIS, L., MISHRA, V., JAIN, P., REIS, R., SAPATNEKAR, S., Uma Abordagem Sistemática para Analisar e Otimizar os Efeitos da Eletromigração nos Sinais Internos das Células, In: XXI IBERCHIP Workshop, Montevideo, February 24-27, 2015

326. TUMELERO, D., BANDEIRA, V., BONTORIN, G., REIS, R., Paralelismo no Roteamento Global de Circuitos VLSI: Estado da Arte, In: XXI IBERCHIP Workshop, Montevideo, February 24-27, 2015.

327. TARRILLO, J., TONFAT, J., TAMBARA, L., KASTENSMIDT, F., REIS, R., Multiple Fault Injection Platform for SRAM-Based FPGA Based on Ground-Level Radiation Experiments, 16th IEEE Latin American Test Symposium, LATS 2015, March 25-27, 2015. DOI: 10.1109/LATW.2015.7102494.

328. GUIMARAES, D., REIS, R., A Mixed Cells Physical Design Approach, IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisboa, Portugal, May 24-27, 2015. P. 1446-1449, ISBN 9781479983902, DOI: 10.1109/ISCAS.2015.7168916

329. TONFAT, J., KASTENSMIDT, F., REIS, R., Energy Efficient Frame-level Redundancy Scrubbing Technique for SRAM-based FPGAs, AHS2015 - 2015 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS, Montreal, Canada, June 15-18, 2015. P. 1-8, ISBN: 978-1-4673-7501-6, DOI: 10.1109/AHS.2015.7231160

330. ZIMPECK, A., KASTENSMIDT, F., REIS, R., Analyzing the Impact of Frequency and Diverse Path Delays in the Time Vulnerability Factor of Master-Slave D Flip-Flops, ISVLSI2015 - IEEE Computer Society Annual Symposium on VLSI, July 8-10, 2015, Montpellier, France. p. 521-526, ISBN: 978-1-4799-8718-4, DOI: 10.1109/ISVLSI.2015.95

331. REIS, R., Trends on EDA for Low Power, NEMO2015, IEEE International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization for RF, Microwave, and Terahertz Applications, August 11-14, 2015, Ottawa, Canadá (Invited Paper).

332. PUGET, J., FLACH, G., JOHANN, M., REIS, R., Jezz: An Effective Legalization Algorithm for Minimum Displacement, 28th Symposium on Integrated Circuits and System Design, SBCCI2015, Salvador, August 31- September 4, 2015. ISBN 978-1-4503-3763-2, DOI: 10.1145/2800986.2801013

333. SANTOS, C., PRIETO, R., VIVET, P., COLONNA, J.-P., COUDRAIN, P., REIS, R., Graphite-based Heat Spreaders for Hotspot Mitigation in 3D ICs, 3DIC – 5th IEEE International Conference on 3D System Integration, August 31- September 2, 2015, Sendai, Japan, DOI: 10.1109/3DIC.2015.7334618

334. CAPUTO, R., SOUSA, D., TERRES, M., BONTORIN, G., REIS, R., JOHANN, M., Energy-Efficient Level Shifter Topology, PATMOS 2015, 25th International Workshop on Power And Timing Modeling, Optimization and Simulation, September 1-4, 2015, Salvador, Brazil. P. 148-151, DOI: 10.1109/PATMOS.2015.7347600

335. GHISSONI, S., COSTA, E, REIS, R., Reusing Smaller Optimized FFT Blocks for the Realization of Larger Power Efficient Radix-2 FFTs, PATMOS 2015, 25th International Workshop on Power And Timing Modeling, Optimization and Simulation, September 1-4, 2015, p. 169-176, Salvador, Brazil. DOI: 10.1109/PATMOS.2015.7347603

336. CHIELLE, E., ROSA, F., RODRIGUES, G., KASTENSMIDT, F., REIS, R., CUENCA-ASENSI, S., Reliability on ARM Processors Against Soft Errors by a Purely Software Approach, RADECS2015, Sept. 14-18, 2015 Moscow, Russia, ISBN: 978-1-5090-0232-0, DOI: 10.1109/RADECS.2015.7365660

337. FLACH, G., MONTEIRO, J., FOGAÇA, M., PUGET, J., JOHANN, M., BUTZEN, P., REIS, R., An Incremental Timing-Driven Placement Flow Using Quadratic Placement Formulation, IFIP/IEEE VLSI-SoC2015, International Conference on Very Large Scale Integration, Daejeon, Korea, October 5-7, 2015

338. ROSA, F., OST, L., KASTENSMIDT, F., REIS, R., A Fast and Scalable Fault Injection Framework to Evaluate Many-core Soft Error Reliability, IEEE DFT 2015, 28th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Amherst, USA, October 12-14, 2015

339. BANDEIRA, V., COSTA, V., BONTORIN, G., REIS, R., Low Latency FPGA Implementation of Izhikevich-Neuron Model, IESS2015 - 5th IFIP International Embedded Systems Symposium, Iguaçu Falls, Brazil, November 3-6, 2015.

340. BARTRA, W., VLADIMIRESCU, A., REIS, R., Bulk and FDSOI Sub-micron CMOS Transistors Resilience to Single-Event Transients, 22nd IEEE International Conference on Electronics, Circuits and Systems – ICECS2015, Cairo, Egypt, December 6 - 9, 2015.

341. POSSER, G., MISHRA, V., JAIN, P., REIS, R., SAPATNEKAR, S., Impact on Performance, Power, Area and Wirelength Using Electromigration-Aware Cells, 22nd IEEE International Conference on Electronics, Circuits and Systems – ICECS2015, Cairo, Egypt, December 6 - 9, 2015.

342. ROSA, F., BRUM, R., OST, L., WIRTH, G., REIS, R., Impact of Dynamic Voltage Scaling and Thermal Factors on FinFET Based SRAM Reliability, 22nd IEEE International Conference on Electronics, Circuits and Systems – ICECS2015, Cairo, Egypt, December 6 - 9, 2015

343. ZIMPECK, A., POSSER, G., REIS, R., MEINHARDT, C., Process Variability in FinFET Standard Cells with Different Transistor Sizing Techniques, 22nd IEEE International Conference on Electronics, Circuits and Systems – ICECS2015, Cairo, Egypt, December 6 - 9, 2015

344. CONCEIÇÃO, C., POSSER, G., REIS, R., Reducing the Number of Transistors with Gate Clustering, Seven IEEE Latin American Symposium on Circuits and Systems – LASCAS 2016, Florianópolis, February 28-March 2, 2016

345. BANDEIRA, V., COSTA, V., BONTORIN, G., REIS, R., Implementação de Baixa Latência do Modelo Simples de Izhikevich em FPGA, Workshop IBERCHIP 2016, Florianópolis, February 28-March 2, 2016

346. SILVA, L., CONCEIÇÃO, C., BONTORIN, G., REIS, R., Minimização Lógica por Fusão de Portas, Workshop IBERCHIP 2016, Florianópolis, February 28-March 2, 2016

347. FLACH, G., FOGAÇA, M., MONTEIRO, J., JOHANN, M., REIS, R., Drive Strength Aware Cell Movement Techniques for Timing Driven Placement, ACM International Symposium on Physical Design, ISPD 2016, Sonoma, USA, April 3-6, 2016.

348. REIMANN, T., SZE, C., REIS, R., Cell Selection for High­Performance Designs in an Industrial Design Flow, ACM International Symposium on Physical Design, ISPD 2016, Sonoma, USA, April 3-6, 2016.

349. PARIS, L., POSSER, G., REIS, R., Electromigration Aware Circuits by Using Special Signal Non-Default Routing Rules, IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal, Canada, May 22-25, 2016.

350. ZIMPECK, A., MEINHARDT, C., POSSER, G., REIS, R., FinFET Cells with Different Transistor Sizing Techniques Against PVT Variations, IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal, Canada, May 22-25, 2016.